SLAS859C May   2012  – May 2015 PCM5100A , PCM5100A-Q1 , PCM5101A , PCM5101A-Q1 , PCM5102A , PCM5102A-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified System Diagram
  5. 5 Revision History
  6. 6 Device Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings Updated ESD Data
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Timing Requirements
    7. 8.7 Timing Requirements, XSMT
    8. 8.8 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Terminology
      2. 9.3.2 Audio Data Interface
        1. 9.3.2.1 Audio Serial Interface
        2. 9.3.2.2 PCM Audio Data Formats
        3. 9.3.2.3 Zero Data Detect
      3. 9.3.3 XSMT Pin (Soft Mute / Soft Un-Mute)
      4. 9.3.4 Audio Processing
        1. 9.3.4.1 Interpolation Filter
      5. 9.3.5 Reset and System Clock Functions
        1. 9.3.5.1 Clocking Overview
        2. 9.3.5.2 Clock Slave Mode With Master/System Clock (SCK) Input (4 Wire I2S)
        3. 9.3.5.3 Clock Slave Mode with BCK PLL to Generate Internal Clocks (3-Wire PCM)
    4. 9.4 Device Functional Modes
      1. 9.4.1 External SCK and PLL Activation
        1. 9.4.1.1 Interpolation Filter Modes
        2. 9.4.1.2 44.1kHz De-emphasis
        3. 9.4.1.3 Audio Format
  10. 10Applications and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Typical Applications
        1. 10.1.1.1 Example Design Requirements
        2. 10.1.1.2 Detailed Design Procedure
        3. 10.1.1.3 Application Curve
  11. 11Power Supply Recommendations
    1. 11.1 Power Supply Distribution and Requirements
    2. 11.2 Recommended Powerdown Sequence
      1. 11.2.1 Planned Shutdown
      2. 11.2.2 Unplanned Shutdown
    3. 11.3 External Power Sense Undervoltage Protection Mode
    4. 11.4 Power-On Reset Function
    5. 11.5 PCM510xA Power Modes
      1. 11.5.1 Setting Digital Power Supplies and I/O Voltage Rails
      2. 11.5.2 Power Save Modes
  12. 12Layout
    1. 12.1 Layout Guidelines
  13. 13Device and Documentation Support
    1. 13.1 Related Links
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
  14. 14Mechanical, Packaging, and Orderable Information
    1. 14.1 Mechanical Data

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Power Supply Recommendations

11.1 Power Supply Distribution and Requirements

The PCM510xA devices are powered through the following pins:

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 pcm5xxx_pwrtree.gifFigure 35. Power Distribution Tree within PCM510xA

Table 12. Power Supply Pin Descriptions

NAME USAGE / DESCRIPTION
AVDD Analog voltage supply; must be 3.3 V. This powers all analog circuitry that the DAC runs on.
DVDD Digital voltage supply. This is used as the I/O voltage control and the input to the onchip LDO.
CPVDD Charge Pump Voltage Supply - must be 3.3 V
LDOO Output from the onchip LDO. Should be used with a 0.1-µF decoupling cap. Can be driven (used as power input) with a 1.8-V supply to bypass the onchip LDO for lower power consumption.
AGND Analog ground
DGND Digital ground

11.2 Recommended Powerdown Sequence

Under certain conditions, the PCM510xA devices can exhibit some pop on power down. Pops are caused by a device not having enough time to detect power loss and start the muting process.

The PCM510xA devices have two auto-mute functions to mute the device upon power loss (intentional or unintentional).

XSMT = 0

When the XSMT pin is pulled low, the incoming PCM data is attenuated to 0, closely followed by a hard analog mute. This process takes 150 sample times (ts) + 0.2 ms.

Because this mute time is mainly dominated by the sampling frequency, systems sampling at 192 kHz will mute much faster than a 48-kHz system.

Clock Error Detect

When clock error is detected on the incoming data clock, the PCM510xA devices switch to an internal oscillator, and continue to the drive the output, while attenuating the data from the last known value. Once this process is complete, the PCM510xA outputs are hard muted to ground.

11.2.1 Planned Shutdown

These auto-muting processes can be manipulated by system designs to mute before power loss in the following ways:

  1. Assert XSMT low 150 tS + 0.2 ms before power is removed.
    2. PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_anti-pop_pwrdwn_seq.gifFigure 36. Assert XSMT
  2. Stop I2S clocks (SCK, BCK, LRCK) 3 ms before powerdown as shown in Figure 37.
    3. PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_anti-pop_pwrdwn_seq2.gifFigure 37. Stop I2C Clocks

11.2.2 Unplanned Shutdown

Many systems use a low-noise regulator to provide an AVDD 3.3-V supply for the DAC. The XSMT Pin can take advantage of such a feature to measure the pre-regulated output from the system SMPS to mute the output before the entire SMPS discharges. Figure 38 shows how to configure such a system to use the XSMT pin. The XSMT pin can also be used in parallel with a GPIO pin from the system microcontroller/DSP or power supply.

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_xsmt_anti_pwrdwnpop.gifFigure 38. Using the XSMT Pin

11.3 External Power Sense Undervoltage Protection Mode

NOTE

External Power Sense Undervoltage Protection Mode is supported only when DVDD = 3.3 V.

The XSMT pin can also be used to monitor a system voltage, such as the 24-VDC LCD TV backlight, or 12-VDC system supply using a voltage divider created with two resistors. (See Figure 39 )

  • If the XSMT pin makes a transition from “1” to “0” over 6 ms or more, the device switches into external under-voltage protection mode. This mode uses two trigger levels:
    • When the XSMT pin level reaches 2 V, soft mute process begins.
    • When the XSMT pin level reaches 1.2 V, analog mute engages, regardless of digital audio level, and analog shutdown begins. (DAC and related circuitry powers down).

If XSMT is moved from "1" to "0" in 20 ns or less, then the device will interpret it as a digital controlled request to mute. It will perform a soft mute, then move to standby.

A timing diagram to show this is shown in Figure 40.

NOTE

The XSMT input pin voltage range is from –0.3 V to DVDD+0.3 V. The ratio of external resistors must produce a voltage within this input range. Any increase in power supply (such as power supply positive noise or ripple) can pull the XSMT pin higher than DVDD+0.3 V.

For example, if the PCM510xA is monitoring a 12-V input, and dividing the voltage by 4, then the voltage at XSMT during ideal power supply conditions is 3.3 V. A voltage spike higher than 14.4 V causes a voltage greater than 3.6 V (DVDD+0.3) on the XSMT pin, potentially damaging the device.

Providing the divider is set appropriately, any DC voltage can be monitored.

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_xsmt_ext_uvp_ckt.gifFigure 39. XSMT in External UVP Mode
PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 f_pcm51xx_td_xsmt_uvp.gifFigure 40. XSMT Timing for Undervoltage Protection

The trigger voltage values for the soft mute and hard mute are shown in Table 13. The range of values will vary from device to device, but typical thresholds are shown. XSMT should be set up to nominally be 3.3 V along with DVDD, but derived from a higher system power supply rail.

Table 13. Distribution of Voltage Thresholds

MIN TYP MAX
Soft Mute Threshold Voltage 2.0 V 2.2 V 0.9×DVDD
Hard Mute Threshold Voltage 0.1×DVDD 0.9 V 1.2 V

11.4 Power-On Reset Function

Power-On Reset, DVDD 3.3-V Supply

The PCM510xA includes a power-on reset function shown in Figure 41. With VDD > 2.8 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state. Analog output will begin ramping after valid data has been passing through the device for the given group delay given by the digital interpolation filter selected.

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 pcm512x4x_por_3p3.gifFigure 41. Power-On Reset Timing, DVDD = 3.3 V

Power-On Reset, DVDD 1.8-V Supply

The PCM510xA includes a power-on reset function shown in Figure 42 operating at DVDD = 1.8 V. With AVDD greater than approximately 2.8 V, CPVDD greater than approximately 2.8 V, and DVDD greater than approximately 1.5 V, the power-on reset function is enabled. After the initialization period, the PCM510xA is set to its default reset state.

PCM5100A PCM5101A PCM5102A PCM5100A-Q1 PCM5101A-Q1 PCM5102A-Q1 pcm512x4x_por_1p8.gifFigure 42. Power-On Reset Timing, DVDD = 1.8 V

11.5 PCM510xA Power Modes

11.5.1 Setting Digital Power Supplies and I/O Voltage Rails

The internal digital core of the PCM510xA devices run from a 1.8-V supply. This can be generated by the internal LDO, or by an external 1.8-V supply.

DVDD is used to set the I/O voltage, and to be used as the input to the onchip LDO that creates the 1.8 V required by the digital core.

For systems that require 3.3 V I/O support, but lower power consumption, DVDD should be connected to 3.3 V and LDOO can be connected to an external 1.8-V source. Doing so will disable the onchip LDO.

When setting I/O voltage to be 1.8 V, both DVDD and LDOO must be provided with an external 1.8-V supply.

11.5.2 Power Save Modes

The PCM510xA devices offer two power-save modes: standby and power-down.

When a clock error (SCK, BCK, and LRCK) or clock halt is detected, the PCM510xA device automatically enters standby mode. The DAC and line driver are also powered down.

When BCK and LRCK remain at a low level for more than 1 second, the PCM510xA device automatically enters powerdown mode. Power-down mode disables the negative charge pump and bias/reference circuit, in addition to those disabled in standby mode.

When expected audio clocks (SCK, BCK, LRCK) are applied to the PCM510xA device, or if BCK and LRCK start correctly while SCK remains at ground level for 16 successive LRCK periods, the device starts its powerup sequence automatically.