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NEW TAD5242 PREVIEW Hardware-control low-power stereo audio DAC with 119-dB dynamic range 8-dB higher performance with integrated headphone amplifier, HW controlled, QFN package

Product details

Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 112 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
Number of DAC channels 2 Analog inputs 0 Analog outputs 2 DAC SNR (typ) (dB) 112 Sampling rate (max) (kHz) 384 Control interface H/W Resolution (Bits) 32 Architecture Delta Sigma with line driver Operating temperature range (°C) -25 to 85 Rating Catalog
TSSOP (PW) 20 41.6 mm² 6.5 x 6.4
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100
  • Ultra Low Out-of-Band Noise
  • Integrated High-Performance Audio PLL with BCK
    Reference to Generate SCK Internally
  • Direct Line Level 2.1-VRMS Output
  • No DC Blocking Capacitors Required
  • Line Level Output Down to 1KΩ
  • Intelligent Muting System; Soft Up or Down Ramp
    and Analog Mute For 120-dB Mute SNR
  • Accepts 16-, 24-, and 32-Bit Audio Data
  • PCM Data Formats: I2S, Left-Justified
  • Automatic Power-Save Mode When LRCK And
    BCK Are Deactivated
  • 1.8 V or 3.3 V Failsafe LVCMOS Digital Inputs
  • Simple Configuration Using Hardware Pins
  • Single-Supply Operation: 14
    • 3.3 V Analog, 1.8 V or 3.3 V Digital
  • Qualified in Accordance with AEC-Q100

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

The PCM510xA devices are a family of monolithic CMOS-integrated circuits that include a stereo digital-to-analog converter and additional support circuitry in a small TSSOP package. The PCM510xA devices use the latest generation of TI’s advanced segment-DAC architecture to achieve excellent dynamic performance and improved tolerance to clock jitter.

Using Directpath™ charge-pump technology, the PCM510xA devices provide 2.1-VRMS ground centered outputs, allowing designers to eliminate DC blocking capacitors on the output, as well as external muting circuits traditionally associated with single-supply line drivers.

The integrated line driver surpasses all other charge-pump based line drivers by supporting loads down to 1 kΩ per pin.

The integrated PLL on the device removes the requirement for a system clock (commonly known as master clock), allowing a 3-wire I2S connection and reducing system EMI.

Intelligent clock error and PowerSense undervoltage protection utilizes a two-level mute system for pop-free performance.

Compared with many conventional switched capacitor DAC architectures, the PCM510xA family offers up to 20 dB lower out-of-band noise, reducing EMI and aliasing in downstream amplifiers/ADCs, measured from the traditional 100-kHz OBN measurements to 3 MHz).

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Technical documentation

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Type Title Date
* Data sheet PCM510xA 2.1 VRMS, 112/106/100 dB Audio Stereo DAC with PLL and 32-bit, 384 kHz PCM Interface datasheet (Rev. C) PDF | HTML 06 May 2015
Circuit design Active-filtering circuit for audio DACs 16 Jan 2019
Circuit design Auxiliary circuits for high-performance audio 16 Jan 2019
EVM User's guide PCM510xEVM-U User Guide (Rev. C) 13 Oct 2014
Application note A Low Noise, Low Distortion Design for Antialiasing and Anti-Imaging Filters 27 Sep 2000

Design & development

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Evaluation board

PCM5102EVM-U — PCM5102 Evaluation Module

The PCM5102EVM-U is a complete evaluation kit for use with a personal computer running the Microsoft Windows™ operating system. The necessary evaluation software can be found online at the PCM5102 Product Folder.

The PCM5102EVM is in the Texas Instruments (TI) EVM form factor, which allows direct (...)

User guide: PDF
Not available on TI.com
Driver or library

PCM5XXX-DRIVERS — PCM5xxx DAC family Linux driver support

The Linux driver supports the PCM51xx device family of audio stereo digital-to-analog converters (DACs), communication through I2C and SPI, and registers with the ASOC framework of the Linux kernel. The "Go to third party" buttons below will allow you to downlod the appropriate drivers from (...)
Simulation model

SBAA346 Companion Simulations

SBAM414.ZIP (55 KB) - TINA-TI Reference Design
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
Package Pins Download
TSSOP (PW) 20 View options

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