SBOS424C March   2008  – November 2015 PGA112 , PGA113 , PGA116 , PGA117

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = AVDD = DVDD = 5 V
    6. 7.6 SPI Timing: VS = AVDD = DVDD = 2.2 V to 5 V
    7. 7.7 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Serial Interface Information
      1. 8.6.1 Serial Digital Interface: SPI Modes
      2. 8.6.2 Serial Digital Interface: SPI Daisy-Chain Communications
      3. 8.6.3 SPI Serial Interface
      4. 8.6.4 SPI Commands
  9. 9 Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Op Amp: Input Stage
      2. 9.1.2 Op Amp: General Gain Equations
      3. 9.1.3 Op Amp: Frequency Response Versus Gain
        1. 9.1.3.1 Example:
      4. 9.1.4 Analog MUX
      5. 9.1.5 System Calibration Using The PGA
      6. 9.1.6 Driving and Interfacing to ADCs
      7. 9.1.7 Power Supplies
      8. 9.1.8 Shutdown and Power-On-Reset (POR)
      9. 9.1.9 Typical Connections: PGA116, PGA117 (TSSOP-20)
    2. 9.2 Typical Applications
      1. 9.2.1 Bipolar Input to Single-Supply Scaling
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Typical Application: General-Purpose Input Scaling
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 High Gain and Wide Bandwidth Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGS|10
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Power Supply Recommendations

Power-supply bypass: Bypass each power-supply pin separately. Use a ceramic capacitor connected directly from the power-supply pin to the ground pin of the IC on the same PCB plane. Vias can then be used to connect to ground and voltage planes. This configuration keeps parasitic inductive paths out of the local bypass for the PGA. Good analog design practice dictates the use of a large value tantalum bypass capacitor on the PCB for each respective voltage.