The PGA112 and PGA113 devices (binary and scope gains) offer two analog inputs, a three-pin SPI interface, and software shutdown in an 10-pin VSSOP package. The PGA116 and PGA117 (binary and scope gains) offer 10 analog inputs, and hardware and software shutdown in a 20-pin TSSOP package.
All versions provide internal calibration channels for system-level calibration. The channels are tied to GND, 0.9 VCAL, 0.1 VCAL, and VREF, respectively. VCAL, an external voltage connected to Channel 0, is used as the system calibration reference. Binary gains are: 1, 2, 4, 8, 16, 32, 64, and 128; scope gains are: 1, 2, 5, 10, 20, 50, 100, and 200.
Featuring low offset, low offset drift and low noise, the PGA11x series provides a flexible analog building block for a variety of applications. The PGA112 and PGA116 offer binary gains of 1, 2, 4, 8, 16, 32, 64, 128 and a 2 channel MUX while the PGA113 and PGA117 offer scope gains of 1, 2, 5, 10, 20, 50, 100, 200 and a 10 channel MUX.
The PGA112 and PGA113 devices have a software shutdown mode, and the PGA116 and PGA117 devices offer both a hardware and software shutdown mode, see Shutdown and Power-On-Reset (POR) for additional information. The PGA uses a standard serial peripheral interface (SPI). Both SPI Mode 0,0 and Mode 1,1 are supported. More information regarding serial communications, including daisy chaining can be found in Serial Interface Information.
|BINARY GAIN (V/V)||TYPICAL
|MODE||CPOL||CPHA||CPOL DESCRIPTION||CPHA DESCRIPTION|
|0, 0||0||0(1)||Clock idles low||Data are read on the rising edge of clock. Data change on the falling edge of clock.|
|1, 1||1||1(2)||Clock idles high||Data are read on the rising edge of clock. Data change on the falling edge of clock.|
If there are not even-numbered increments of 16 clocks (that is, 16, 32, 64, and so forth) between CS going low (falling edge) and CS going high (rising edge), the device takes no action. This condition provides reliable serial communication. Furthermore, this condition also provides a way to quickly reset the SPI interface to a known starting condition for data synchronization. Transmitted data are latched internally on the rising edge of CS.
On the PGA116 and PGA117 devices, CS, DIN, and SCLK are Schmitt-triggered CMOS logic inputs. DIN has a weak internal pulldown to support daisy-chain communications on the PGA116 and PGA117 devices. DOUT is a CMOS logic output. When CS is high, the state of DOUT is high-impedance. When CS is low, DOUT is driven as illustrated in Figure 57.
On the PGA112 and PGA113 devices, there are digital output and digital input gates both internally connected to the DIO pin. DIN is an input-only gate and DOUT is a digital output that can give a 3-state output. The DIO pin has a weak 10-μA pulldown current source to prevent the pin from floating in systems with a high-impedance SPI DOUT line. When CS is high, the state of the internal DOUT gate is high-impedance. When CS is low, the state of DIO depends on the previous valid SPI communication; either DIO becomes an output to clock out data or it remains an input to receive data. This structure is shown in Figure 58.
To reduce the number of I/O port pins used on a microcontroller, the PGA116 and PGA117 support SPI daisy-chain communications with full read and write capability. A two-device daisy-chain configuration is shown in Figure 59, although any number of devices can be daisy-chained. The SPI daisy-chain communication uses a common SCLK and CS line for all devices in the daisy chain, rather than each device requiring a separate CS line. The daisy-chain mode of communication routes data serially through each device in the chain by using its respective DIN and DOUT pins as shown. Special commands are used (see Table 4) to ensure that data are written or read in the proper sequence. There is a special daisy-chain NOP command (No OPeration) which, when presented to the desired device in the daisy-chain, causes no changes in that respective device. Detailed timing diagrams for daisy-chain operation are shown in Figure 63 through Figure 65.
The PGA112 and PGA113 devices can be used as the last device in a daisy-chain as shown in Figure 60 if write-only communication is acceptable, because the PGA112 and PGA113 devices have no separate DOUT pin to connect back to the microcontroller DIN pin to read back data in this configuration.
The maximum SCLK frequency that can be used in daisy-chain operation is directly related to SCLK rise and fall times, DIN setup time, and DOUT propagation delay. Any number of two or more devices have the same limitations because it is the timing considerations between adjacent devices that limit the clock speed.
Figure 61 analyzes the maximum SCLK frequency for daisy-chain mode based on the circuit of Figure 59. A clock rise and fall time of 10 ns is assumed to allow for extra bus capacitance that could occur as a result of multiple devices in the daisy-chain.
|D15||D14||D13||D12||D11||D10||D9||D8||D7||D6||D5||D4||D3||D2||D1||D0||THREE-WIRE SPI COMMAND|
|G3||G2||G1||G0||BINARY GAIN||SCOPE GAIN|
|CH3||CH2||CH1||CH0||PGA112, PGA113||PGA116, PGA117|
|1||0||1||1||Factory Reserved||Factory Reserved|