SBOS424C March   2008  – November 2015 PGA112 , PGA113 , PGA116 , PGA117


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: VS = AVDD = DVDD = 5 V
    6. 7.6 SPI Timing: VS = AVDD = DVDD = 2.2 V to 5 V
    7. 7.7 Typical Characteristics
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
    6. 8.6 Serial Interface Information
      1. 8.6.1 Serial Digital Interface: SPI Modes
      2. 8.6.2 Serial Digital Interface: SPI Daisy-Chain Communications
      3. 8.6.3 SPI Serial Interface
      4. 8.6.4 SPI Commands
  9. Applications and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Op Amp: Input Stage
      2. 9.1.2 Op Amp: General Gain Equations
      3. 9.1.3 Op Amp: Frequency Response Versus Gain
        1. Example:
      4. 9.1.4 Analog MUX
      5. 9.1.5 System Calibration Using The PGA
      6. 9.1.6 Driving and Interfacing to ADCs
      7. 9.1.7 Power Supplies
      8. 9.1.8 Shutdown and Power-On-Reset (POR)
      9. 9.1.9 Typical Connections: PGA116, PGA117 (TSSOP-20)
    2. 9.2 Typical Applications
      1. 9.2.1 Bipolar Input to Single-Supply Scaling
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      2. 9.2.2 Typical Application: General-Purpose Input Scaling
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 High Gain and Wide Bandwidth Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

11 Layout

11.1 Layout Guidelines

11.1.1 High Gain and Wide Bandwidth Considerations

As a result of the combination of wide bandwidth and high gain capability of the PGA112 and PGA113 devices and PGA116 and PGA117 devices, there are several printed-circuit-board (PCB) design and system recommendations to consider for optimum application performance.

  1. Power-supply bypass: Refer to Power Supply Recommendations.
  2. Signal trace routing: Keep VOUT and other low impedance traces away from MUX channel inputs that are high impedance. Poor signal routing can cause positive feedback, unwanted oscillations, or excessive overshoot and ringing on step-changing signals. If the input signals are particularly noisy, separate MUX input channels with guard traces on either side of the signal traces. Connect the guard traces to ground near the PGA and at the signal entry point into the PCB. On multilayer PCBs, ensure that there are no parallel traces near MUX input traces on adjacent layers; capacitive coupling from other layers can be a problem. Use ground planes to isolate MUX input signal traces from signal traces on other layers.
  3. Additionally, group and route the digital signals into the PGA as far away as possible from the analog MUX input signals. Most digital signals are fast rise and fall time signals with low-impedance drive capability that can easily couple into the high-impedance inputs of the input MUX channels. This coupling can create unwanted noise that gains up to VOUT.

  4. Input MUX channels and source impedance: Input MUX channels are high-impedance; when combined with high gain, the channels can pick up unwanted noise. Keep the input signal sources low-impedance
    (< 10 kΩ). Also, consider bypassing input MUX channels with a ceramic bypass capacitor directly at the MUX input pin. Bypass capacitors greater than 100 pF are recommended. Lower impedances and a bypass capacitor placed directly at the input MUX channels keep crosstalk between channels to a minimum as a result of parasitic capacitive coupling from adjacent PCB traces and pin-to-pin capacitance.

11.2 Layout Example

PGA112 PGA113 PGA116 PGA117 PGA112_Layout_Example_SBOS424.gif Figure 82. PGA11x Layout Example