SBOSAE0B April   2023  – September 2023 PGA855

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Device Comparison Table
  7. 6 Pin Configuration and Functions
  8. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Gain Control
      2. 8.3.2 Input Protection
      3. 8.3.3 Output Common-Mode Pin
      4. 8.3.4 Using the Fully Differential Output Amplifier to Shape Noise
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Linear Operating Input Range
    2. 9.2 Typical Applications
      1. 9.2.1 ADS127L11 and ADS127L21, 24-Bit, Delta-Sigma ADC Driver Circuit
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 ADS8900B 20-Bit SAR ADC Driver Circuit
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Development Support
        1. 10.1.1.1 PSpice® for TI
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 Receiving Notification of Documentation Updates
    4. 10.4 Support Resources
    5. 10.5 Trademarks
    6. 10.6 Electrostatic Discharge Caution
    7. 10.7 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9.2.1.2 Detailed Design Procedure

Table 9-2 and Table 9-3 show the typical signal-to-noise (SNR) and total harmonic distortion (THD) of the PGA855 driving the ADS127Lx1 delta-sigma ADC using a sinc4 or wideband filter. Figure 9-7 and Figure 9-8 show the respective FFT plots. For the SNR and THD measurements, a 1‑kHz differential signal is applied. The signal amplitude is adjusted to produce a PGA855 output at –0.2 dBFS of the ADC full-scale range. For a list of the equivalent input voltage amplitude signals for the different PGA855 gain configurations, see Table 9-2 and Table 9-3. At gain = 1 V/V, the design achieves –121.4‑dB THD and 109.1‑dB SNR.

Table 9-2 PGA855 and ADS127Lx1 FFT Data Summary, OSR = 64, Sinc4 Filter
PGA GAIN (V/V) INPUT AMPLITUDE (VPP) SNR (dB) THD (dB) ENOB (Bits)
0.125 40.0 106.0 –119.6 17.5
0.25 32.022 109.0 –119.3 17.8
0.5 16.012 109.8 –121.2 17.9
1 8.006 109.6 –121.4 17.9
2 4.002 109.6 –121.4 17.9
4 2.002 107.4 –121.4 17.5
8 1.0 104.0 –121.4 17.0
16 0.5 99.1 –117.0 16.2
Table 9-3 PGA855 and ADS127Lx1 FFT Data Summary, OSR = 64, Wideband Filter
PGA GAIN (V/V) INPUT AMPLITUDE (VPP) SNR (dB) THD (dB) ENOB (Bits)
0.125 40.0 106.0 –119.6 17.3
0.25 32.022 107.5 –119.0 17.5
0.5 16.012 107.7 –121.2 17.6
1 8.006 107.6 –121.4 17.6
2 4.002 107.0 –121.4 17.5
4 2.002 105.4 –121.4 17.2
8 1.0 101.7 –121.4 16.6
16 0.5 96.7 –117.0 15.8

The R-C-R differential low-pass filter at the input of the instrumentation amplifier helps reduce EMI/RFI high-frequency extrinsic noise. This filter can be customized per the bandwidth and application requirements. This design example (see Figure 9-6) suggests a filter with the capacitor ratio of CIN_DIFF = 10 × CIN_CM. Using the 10-to-1 ratio for differential capacitor CIN_DIFF versus common-mode capacitors CIN_CM offers good differential and common-mode noise rejection, and this arrangement tends to be less sensitive to the tolerance variation and mismatch of the filter capacitors.

The feedback capacitor, CFB, is in parallel with the PGA855 output-stage 5-kΩ feedback resistors to implement additional noise filtering. The internal resistors have ±15 % absolute resistance variation, and this variation must be taken in to account when implementing noise filtering. In this example, CFB is set to 25 pF, providing a typical f–3dB corner frequency of 1 MHz. The estimated minimum f–3dB corner frequency for this circuit is approximately 938 kHz when accounting for the feedback-resistor variation.

The filter at the ADS127Lx1 inputs works as a charge reservoir to filter the sampled input of the ADC. The charge reservoir reduces the instantaneous charge demand of the amplifier, maintaining low distortion and low gain error that otherwise can degrade because of incomplete amplifier settling. The ADC input filter values are RFIL = 47.4 Ω, CDIFF = 560 pF, and CCM = 51 pF. The ADC input precharge buffers significantly reduce the sample-phase input charge that raises the ADC input impedance to decrease gain error.

High-grade COG (NPO) are used everywhere in the signal path (CIN_DIFF, CIN_CM, CFB, CDIFF, CCM) for low distortion. Among ceramic surface-mount capacitors, COG (NPO) ceramic capacitors provide the best capacitance accuracy. The type of dielectric used in COG (NPO) ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.