SNAS795A February   2020  – July 2020 REF4132-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
      2.      Dropout vs. Current Load Over Temperature
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1      Absolute Maximum Ratings
    2. 7.2      ESD Ratings
    3. 7.3      Recommended Operating Conditions
    4. 7.4      Thermal Information
    5. Table 1. Electrical Characteristics
    6. 7.5      Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Solder Heat Shift
    2. 8.2 Long-Term Stability
    3. 8.3 Thermal Hysteresis
    4. 8.4 Power Dissipation
    5. 8.5 Noise Performance
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Supply Voltage
      2. 9.3.2 Low Temperature Drift
      3. 9.3.3 Load Current
    4. 9.4 Device Functional Modes
      1. 9.4.1 EN Pin
      2. 9.4.2 Negative Reference Voltage
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application: Basic Voltage Reference Connection
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Input and Output Capacitors
        2. 10.2.2.2 VIN Slew Rate Considerations
        3. 10.2.2.3 Shutdown/Enable Feature
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Support Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12.1 Layout Guidelines

Figure 31 illustrates an example of a PCB layout for a data acquisition system using the REF4132-Q1. Some key considerations are:

  • Connect low-ESR, 0.1-μF ceramic bypass capacitors at VIN, VREF of the REF4132-Q1.
  • Decouple other active devices in the system per the device specifications.
  • Using a solid ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise pickup.
  • Place the external components as close to the device as possible. This configuration prevents parasitic errors (such as the Seebeck effect) from occurring.
  • Do not run sensitive analog traces in parallel with digital traces. Avoid crossing digital and analog traces if possible, and only make perpendicular crossings when absolutely necessary.