SLLSE11H March   2012  – March 2019 SN65HVD72 , SN65HVD75 , SN65HVD78


  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Typical Application Diagram
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Power Dissipation
    7. 7.7  Switching Characteristics: 250 kbps Device (SN65HVD72) Bit Time ≥ 4 µs
    8. 7.8  Switching Characteristics: 20 Mbps Device (SN65HVD75) Bit Time ≥50 ns
    9. 7.9  Switching Characteristics: 50 Mbps Device (SN65HVD78) Bit Time ≥20 ns
    10. 7.10 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
        1. Data Rate and Bus Length
        2. Stub Length
        3. Bus Loading
        4. Receiver Failsafe
        5. Transient Protection
      2. 10.2.2 Detailed Design Procedure
        1. External Transient Protection
        2. Isolated Bus Node Design
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Documentation Support
      1. 13.2.1 Related Documentation
    3. 13.3 Related Links
    4. 13.4 Community Resources
    5. 13.5 Trademarks
    6. 13.6 Electrostatic Discharge Caution
    7. 13.7 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Isolated Bus Node Design

Many RS-485 networks use isolated bus nodes to prevent the creation of unintended ground loops and their disruptive impact on signal integrity. An isolated bus node typically includes a microcontroller that connects to the bus transceiver via a multi-channel, digital isolator (Figure 27).

SN65HVD72 SN65HVD75 SN65HVD78 iso_app_llse11.gifFigure 27. Isolated Bus Node with Transient Protection

Power isolation is accomplished using the push-pull transformer driver SN6501 and a low-cost LDO, TLV70733.

Signal isolation uses the quadruple digital isolator ISO7241. Notice that both enable inputs, EN1 and EN2, are pulled up via 4.7 kΩ resistors to limit their input currents during transient events.

While the transient protection is similar to the one in Figure 26 (left circuit), an additional high-voltage capacitor is used to divert transient energy from the floating RS-485 common further towards Protective Earth (PE) ground. This is necessary as noise transients on the bus are usually referred to Earth potential.

RHV refers to a high voltage resistor, and in some applications even a varistor. This resistance is applied to prevent charging of the floating ground to dangerous potentials during normal operation.

Occasionally varistors are used instead of resistors to rapidly discharge CHV, if it is expected that fast transients might charge CHV to high-potentials.

Note that the PE island represents a copper island on the PCB for the provision of a short, thick Earth wire connecting this island to PE ground at the entrance of the power supply unit (PSU).

In equipment designs using a chassis, the PE connection is usually provided through the chassis itself. Typically the PE conductor is tied to the chassis at one end while the high-voltage components, CHV and RHV, are connecting to the chassis at the other end.