SLLSED6B October   2012  – November 2017 SN65HVD82


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Receiver Failsafe
      2. 8.3.2 Low-Power Standby Mode
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Device Configuration
      2. 9.1.2 Bus - Design
      3. 9.1.3 Cable-Length Versus Data Rate
      4. 9.1.4 Stub - Length
      5. 9.1.5 3-V to 5-V Interface
      6. 9.1.6 Noise Immunity
      7. 9.1.7 Transient Protection
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. Custom Design With WEBENCH® Tools
        2. Isolated Bus Node Design
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Design and Layout Considerations For Transient Protection
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Third-Party Products Disclaimer
      2. 12.1.2 Custom Design With WEBENCH® Tools
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Detailed Description


The SN65HVD82 device is a half-duplex RS-485 transceiver suitable for data transmission at rates up to 250 kbps over controlled-impedance transmission media (such as twisted-pair cabling). The device features a high level of internal transient protection, making it able to withstand up ESD strikes up to 12 kV (per IEC 61000-4-2) and EFT transients up to 4 kV (per IEC 61000-4-4) without incurring damage. Up to 256 units of SN65HVD82 may share a common RS-485 bus due to the device’s low bus input currents. The device also features a low standby current consumption of 400 nA (typical).

Functional Block Diagram

SN65HVD82 logic_diag_llsed6.gif Figure 13. Logic Diagram (Positive Logic)

Feature Description

Receiver Failsafe

The differential receiver is failsafe to invalid bus states caused by:

  • open bus conditions such as a disconnected connector
  • shorted bus conditions such as cable damage shorting the twisted-pair together, or
  • idle bus conditions that occur when no driver on the bus is actively driving
In any of these cases, the differential receiver will output a failsafe logic High state so that the output of the receiver is not indeterminate.

Receiver failsafe is accomplished by offsetting the receiver thresholds so that the “input indeterminate” range does not include zero volts differential.  In order to comply with the RS-422 and RS-485 standards, the receiver output must output a High when the differential input VID is more positive than 200 mV, and must output a Low when the VID is more negative than –200 mV.  The receiver parameters which determine the failsafe performance are VIT+ and VIT– and VHYS.  As seen in the Electrical Characteristics table, differential signals more negative than
–200 mV will always cause a Low receiver output.  Similarly, differential signals more positive than 200 mV will always cause a High receiver output.

When the differential input signal is close to zero, it will still be above the VIT+ threshold, and the receiver output will be High.  Only when the differential input is more negative than VIT– will the receiver output transition to a Low state.  So the noise immunity of the receiver inputs during a bus fault condition includes the receiver hysteresis value VHYS (the separation between VIT+ and VIT– ) as well as the value of VIT+.

Signals which transition from positive to negative (or from negative to positive) will transition only once, ensuring no spurious bits.

Low-Power Standby Mode

When both the driver and receiver are disabled (DE transitions to a low state and RE transitions to a high state) the device enters standby mode. If the enable inputs are in this state for a brief time (e.g. less than 100 ns), the device does not enter standby mode. This prevents inadvertently entering standby mode during driver/receiver enabling. Only when the enable inputs are held in this state a sufficient duration (e.g. for 300 ns or more), the device is assured to be in standby mode. In this low-power standby mode, most internal circuitry is powered down, and the steady-state supply current is typically less than 400 nA. When either the driver or the receiver is re-enabled, the internal circuitry becomes active.

Device Functional Modes

Table 1. Driver Function Table

H H H L Actively drive bus High
L H L H Actively drive bus Low
X L Z Z Driver disabled
X OPEN Z Z Driver disabled by default
OPEN H H L Actively drive bus High by default

Table 2. Receiver Function Table

VIT+ < VID L H Receive valid bus High
VIT– < VID < VIT+ L ? Indeterminate bus state
VID < VIT– L L Receive valid bus Low
X H Z Receiver disabled
X OPEN Z Receiver disabled by default
Open-circuit bus L H Fail-safe high output
Short-circuit bus L H Fail-safe high output
Idle (terminated) bus L H Fail-safe high output
SN65HVD82 inp-outp_llsed6.gif Figure 14. Equivalent Input and Output Schematic Diagrams