SLLS362G SEPTEMBER   1999  – January 2016 SN65LVDS387 , SN65LVDS389 , SN65LVDS391 , SN75LVDS387 , SN75LVDS389 , SN75LVDS391


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (Continued)
  6. Device Options
  7. Pin Configuration and Functions
  8. Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Switching Characteristics
    7. 8.7 Typical Characteristics
  9. Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Driver Output Voltage and Power-On Reset
      2. 10.3.2 5-V Input Tolerance
      3. 10.3.3 NC Pins
      4. 10.3.4 Unused Enable Pins
      5. 10.3.5 Driver Equivalent Schematics
    4. 10.4 Device Functional Modes
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Signaling Rate vs Distance
    2. 11.2 Typical Application
      1. 11.2.1 Point-to-Point Communications
        1. Design Requirements
        2. Detailed Design Procedure
          1. Driver Supply Voltage
          2. Driver Bypass Capacitance
          3. Driver Output Voltage
          4. Interconnecting Media
          5. PCB Transmission Lines
          6. Termination Resistor
          7. Driver NC Pins
        3. Application Curve
      2. 11.2.2 Multidrop Communications
        1. Design Requirements
        2. Detailed Design Procedure
          1. Interconnecting Media
        3. Application Curve
  12. 12Power Supply Recommendations
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Microstrip vs Stripline Topologies
      2. 13.1.2 Dielectric Type and Board Construction
      3. 13.1.3 Recommended Stack Layout
      4. 13.1.4 Separation Between Traces
      5. 13.1.5 Crosstalk and Ground Bounce Minimization
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Third-Party Products Disclaimer
      2. 14.1.2 Other LVDS Products
    2. 14.2 Documentation Support
      1. 14.2.1 Related Information
    3. 14.3 Related Links
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • PW|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Detailed Description

10.1 Overview

The SNx5LVDSxx devices are quad-, eight-, and 16-channel LVDS line drivers. They operate from a single supply that is nominally 3.3 V, but can be as low as 3 V and as high as 3.6 V. The input signals to the SNx5LVDSxx device are LVTTL signals. The outputs of the device are differential signals complying with the LVDS standard (TIA/EIA-644A). The differential output signal operates with a signal level of 340 mV, nominally, at a common-mode voltage of 1.2 V. This low differential output voltage results in a low emitted radiated energy, which is dependent on the signal slew rate. The differential nature of the output provides immunity to common-mode coupled signals.

The SNx5LVDSxx device is intended to drive a 100-Ω transmission line. This transmission line may be a printed-circuit board (PCB) or cabled interconnect. With transmission lines, the optimum signal quality and power delivery is reached when the transmission line is terminated with a load equal to the characteristic impedance of the interconnect. Likewise, the driven 100-Ω transmission line should be terminated with a matched resistance.

10.2 Functional Block Diagram

SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 log_dia_lls362.gif Figure 14. Logic Diagram (Positive Logic)

10.3 Feature Description

10.3.1 Driver Output Voltage and Power-On Reset

The SNx5LVDSxx driver operates and meets all the specified performance requirements for supply voltages in the range of 3.0 V to 3.6 V. When the supply voltage drops below 1.5 V (or is turning on and has not yet reached 1.5 V), power-on reset circuitry sets the driver output to a high-impedance state.

10.3.2 5-V Input Tolerance

5-V and 3.3-V TTL logic standards share the same input high-voltage and input low-voltage thresholds, namely 2.0 V and 0.8 V, respectively. Although the maximum supply voltage for the SNx5LVDSxx is 3.6 V, the driver can operate and meet all performance requirements when the input signals are as high as 5 V. This allows operation with 3.3-V TTL as well as 5-V TTL logic. 3.3-V CMOS and 5-V CMOS inputs are also allowable, although one should ensure that the duty-cycle distortion that will result from the TTL (ground-referenced) thresholds are acceptable.

10.3.3 NC Pins

NC (not connected) pins are pins where the die is not physically connected to the lead frame or package. For optimum thermal performance, a good rule of thumb is to ground the NC pins at the board level.

10.3.4 Unused Enable Pins

Unused enable pins should be tied to VCC or GND as appropriate.

10.3.5 Driver Equivalent Schematics

The SNx5LVDSxx equivalent output schematic diagrams are shown in Figure 15. The driver input is represented by a CMOS inverter stage with a 7-V Zener diode. The input stage is high-impedance, and includes an internal pulldown to ground. If the driver input is left open, the driver input provides a low-level signal to the rest of the driver circuitry, resulting in a low-level signal at the driver output pins. The Zener diode provides ESD protection. The driver output stage is a differential pair, one half of which is shown in Figure 15. Like the input stage, the driver output includes Zener diodes for ESD protection. The schematic shows an output stage that includes a set of current sources (nominally 3.5 mA) that are connected to the output load circuit based upon the input stage signal. To the first order, the SNx5LVDSxx output stage acts a constant-current source.

SN65LVDS387 SN75LVDS387 SN65LVDS389 SN75LVDS389 SN65LVDS391 SN75LVDS391 sche_dia_lls362.gif Figure 15. Equivalent Input and Output Schematic Diagrams

10.4 Device Functional Modes

Table 1 provides the truth table for the SNx5LVDSxx devices.

Table 1. Driver Function Table(1)

(1) H = high-level, L = low-level, X = irrelevant, Z = high-impedance (off)