Quad LVDS driver
Product details
Parameters
Package | Pins | Size
Features
- Four (’391), Eight (’389), or Sixteen (’387) Line
Drivers Meet or Exceed the Requirements of ANSI
EIA/TIA-644 Standard - Designed for Signaling Rates Up to 630 Mbps
With Very Low Radiation (EMI) - Low-Voltage Differential Signaling With Typical
Output Voltage of 350 mV and a 100-Ω Load - Propagation Delay Times Less Than 2.9 ns
- Output Skew Is Less Than 150 ps
- Part-to-Part Skew Is Less Than 1.5 ns
- 35-mW Total Power Dissipation in Each Driver
Operating at 200 MHz - Driver Is High-Impedance When Disabled or With
VCC < 1.5 V - SN65’ Version Bus-Pin ESD Protection Exceeds
15 kV - Packaged in Thin Shrink Small-Outline Package
With 20-mil Pin Pitch - Low-Voltage TTL (LVTTL) Logic Inputs Are 5-V
Tolerant
Description
This family of 4, 8, and 16 differential line drivers implements the electrical characteristics of low-voltage differential signaling (LVDS). This signaling technique lowers the output voltage levels of 5-V differential standard levels (such as EIA/TIA-422B) to reduce the power, increase the switching speeds, and allow operation with a 3.3-V supply rail. Any of the 16 current-mode drivers will deliver a minimum differential output voltage magnitude of 247 mV into a 100-Ω load when enabled.
When disabled, the driver outputs are high-impedance. Each driver input (A) and enable (EN) have an internal pulldown that will drive the input to a low level when open-circuited.
The SN65LVDS387, SN65LVDS389, and SN65LVDS391 devices are characterized for operation from –40°C to 85°C. The SN75LVDS387, SN75LVDS389, and SN75LVDS391 devices are characterized for operation from 0°C to 70°C.
Technical documentation
Type | Title | Date | |
---|---|---|---|
* | Datasheet | SNx5LVDS3xx High-Speed Differential Line Drivers datasheet (Rev. G) | Jan. 14, 2016 |
Application note | LVDS to Improve EMC in Motor Drives | Sep. 27, 2018 | |
Application note | How Far, How Fast Can You Operate LVDS Drivers and Receivers? | Aug. 03, 2018 | |
Application note | How to Terminate LVDS Connections with DC and AC Coupling | May 16, 2018 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.Design tools & simulation
Features
- Leverages Cadence PSpice Technology
- Preinstalled library with a suite of digital models to enable worst-case timing analysis
- Dynamic updates ensure you have access to most current device models
- Optimized for simulation speed without loss of accuracy
- Supports simultaneous analysis of multiple products
- (...)
CAD/CAE symbols
Package | Pins | Download |
---|---|---|
SOIC (D) | 16 | View options |
TSSOP (PW) | 16 | View options |
Ordering & quality
- RoHS
- REACH
- Device marking
- Lead finish/Ball material
- MSL rating/Peak reflow
- MTBF/FIT estimates
- Material content
- Qualification summary
- Ongoing reliability monitoring
Support & training
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