SCAS956D May   2023  – March 2024 SN74AC244-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Switching Characteristics 1.5-V VCC
    7. 5.7  Switching Characteristics 1.8-V VCC
    8. 5.8  Switching Characteristics 2.5-V VCC
    9. 5.9  Switching Characteristics 3.3-V VCC
    10. 5.10 Switching Characteristics 5-V VCC
    11. 5.11 Noise Characteristics
    12. 5.12 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Balanced CMOS 3-State Outputs
      2. 7.3.2 Standard CMOS Inputs
      3. 7.3.3 Clamp Diode Structure
      4. 7.3.4 Wettable Flanks
    4. 7.4 Device Functional Modes
  9. 8 Application Information Disclaimer
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. 8.2.1.1 Power Considerations
        2. 8.2.1.2 Input Considerations
        3. 8.2.1.3 Output Considerations
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RKS|20
  • DGS|20
  • PW|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

3 Description

The SN74AC244-Q1 is an octal buffer with 3-state outputs and Schmitt-trigger inputs. The device is configured into two banks of four drivers, each controlled by an output enable pin.

Package Information
PART NUMBER PACKAGE(1) PACKAGE SIZE(2) BODY SIZE(3)
SN74AC244-Q1 DGS (VSSOP, 20) 5.1mm × 4.9mm 5.1mm × 3mm
RKS (VQFN, 20) 4.5mm × 2.5mm 4.5mm × 2.5mm
PW (TSSOP, 20) 6.5mm × 6.4mm 6.5mm × 4.4mm
(1) For more information, see Section 11.
(2) The package size (length × width) is a nominal value and includes pins, where applicable.
(3) The body size (length × width) is a nominal value and does not include pins.
GUID-20211228-SS0I-Z7ZX-PZSM-JF5WJZR8FXPZ-low.gif Logic Diagram (Positive Logic)