SCLS256L December   1995  – November 2016 SN54AHC125 , SN74AHC125

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics: VCC = 3.3 V ±0.3 V
    7. 6.7  Switching Characteristics: VCC = 5 V ±0.5 V
    8. 6.8  Noise Characteristics
    9. 6.9  Operating Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|14
  • RGY|14
  • DB|14
  • DGV|14
  • PW|14
  • N|14
  • NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • Operating Range: 2 V to 5.5 V
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • Four Individual Output Enable Pins
  • All Inputs Have Schmitt-Trigger Action

Applications

  • Flow Meters
  • Programmable Logic Controllers
  • Power Over Ethernet (PoE)
  • Motor Drives and Controls
  • Electronic Point-of-Sale

Description

The SNx4AHC125 devices are quadruple bus buffer gates featuring independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is high. When OE is low, the respective gate passes the data from the A input to its Y output.

To ensure the high-impedance state during power up or power down, OE must be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Device Information(1)

PART NUMBER PACKAGE (PINS) BODY SIZE (NOM)
SNx4AHC125FK LCCC (20) 8.89 mm 8.89 mm
SNx4AHC125DB SSOP (14) 6.20 mm 5.30 mm
SNx4AHC125D SOIC (14) 8.65 mm × 3.91 mm
SNx4AHC125NS SO (14) 10.30 mm × 5.30 mm
SNx4AHC125W CFP (14) 9.21 mm × 5.97 mm
SNx4AHC125DGV TVSOP (14) 3.60 mm × 4.40 mm
SNx4AHC125PW TSSOP (14) 5.00 mm × 4.40 mm
SNx4AHC125N PDIP (14) 19.30 mm × 6.35 mm
SNx4AHC125RGY VQFN (14) 3.50 mm × 3.50 mm
SNx4AHC125J CDIP (14) 19.56 mm × 6.67 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram (Positive Logic)

SN54AHC125 SN74AHC125 logic_cls256.gif
Pin numbers shown are for the D, DB, DGV, J, N, NS, PW, RGY, and W packages.