SCES905D July   2019  – September 2021 SN74AXC4T245-Q1

PRODUCTION DATA  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Switching Characteristics, VCCA = 0.7 V ± 0.05 V
    7. 6.7  Switching Characteristics, VCCA = 0.8 V ± 0.04 V
    8. 6.8  Switching Characteristics, VCCA = 0.9 V ± 0.045 V
    9. 6.9  Switching Characteristics, VCCA = 1.2 V ± 0.1 V
    10. 6.10 Switching Characteristics, VCCA = 1.5 V ± 0.1 V
    11. 6.11 Switching Characteristics, VCCA = 1.8 V ± 0.15 V
    12. 6.12 Switching Characteristics, VCCA = 2.5 V ± 0.2 V
    13. 6.13 Switching Characteristics, VCCA = 3.3 V ± 0.3 V
    14. 6.14 Operating Characteristics: TA = 25°C
    15. 6.15 Typical Characteristics
  7. Parameter Measurement Information
    1. 7.1 Load Circuit and Voltage Waveforms
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Standard CMOS Inputs
      2. 8.3.2  Balanced High-Drive CMOS Push-Pull Outputs
      3. 8.3.3  Partial Power Down (Ioff)
      4. 8.3.4  VCC Isolation
      5. 8.3.5  Over-Voltage Tolerant Inputs
      6. 8.3.6  Glitch-Free Power Supply Sequencing
      7. 8.3.7  Negative Clamping Diodes
      8. 8.3.8  Fully Configurable Dual-Rail Design
      9. 8.3.9  Supports High-Speed Translation
      10. 8.3.10 Wettable Flanks
    4. 8.4 Device Functional Modes
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Support Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • AEC-Q100 qualified for automotive applications
  • Available in wettable flank QFN (WBQB) package
  • Fully-configurable dual-rail design allows each port to operate with a power supply range from 0.65 V to 3.6 V
  • Operating temperature from –40°C to +125°C
  • Multiple direction control pins to allow simultaneous up and down translation
  • Glitch-free power supply sequencing
  • Up to 380 Mbps support when translating from 1.8 V to 3.3 V
  • VCC isolation feature:
    • If either VCC input is below 100 mV, all I/O outputs are disabled and become high impedance
  • Ioff supports partial-power-down mode operation
  • Compatible with AVC-family level shifters
  • Latch-up performance exceeds 100 mA per JESD 78, class II
  • ESD protection exceeds JEDEC JS-001
    • 8000-V human-body model
    • 1000-V charged-device model