The SN74HC164 is an 8-bit shift register with 2 serial inputs (A and B) connected through an AND gate, as well as an asynchronous clear (CLR). The device requires a high signal on both A and B in order to set the input data line high; a low signal on either input will set the input data line low. Data at A and B can be changed while CLK is high or low, provided that the minimum set-up time requirements are met.
The CLK pin of the SN74HC164 is triggered on a positive or rising-edge signal, from LOW to HIGH. Upon a positive-edge trigger, the device will store the result of the (A ● B) input data line in the first register and propagate each register’s data to the next register. The data of the last register, QH, will be discarded at each clock trigger. If a low signal is applied to the CLR pin of the SN74HC164, the device will set all registers to a value of 0 immediately.
The HC164 has a wide operating voltage range of 2 V to 6 V, outputs that can drive up to 10 LSTTL loads and Low Power Consumption, 80-μA maximum I. It is typically tpd = 20 ns and has ±4-mA output drive at 5 V with low input current of 1-μA maximum. It also has AND-gated (enable/disable) serial inputs a fully buffered clock and serial inputs as well as a direct clear.
Table 1 lists the functional modes of the SNx4HC164.
|CLR||CLK||A||B||QA||QB||. . .||QH|