SCLS116H December   1982  – December 2015 SN54HC165 , SN74HC165

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics, TA = 25°C
    6. 6.6  Electrical Characteristics, SN54HC165
    7. 6.7  Electrical Characteristics, SN74HC165
    8. 6.8  Switching Characteristics, TA = 25°C
    9. 6.9  Switching Characteristics, SN54HC165
    10. 6.10 Switching Characteristics, SN74HC165
    11. 6.11 Timing Requirements, TA = 25°C
    12. 6.12 Timing Requirements, SN54HC165
    13. 6.13 Timing Requirements, SN74HC165
    14. 6.14 Operating Characteristics
    15. 6.15 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Table
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Community Resources
      1. 12.3.1 Trademarks
      2. 12.3.2 Electrostatic Discharge Caution
    4. 12.4 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DB|16
  • PW|16
  • NS|16
  • N|16
  • D|16
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive Up to 10 LSTTL Loads
  • Low Power Consumption, 80-µA Maximum ICC
  • Typical tpd = 13 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Maximum
  • Complementary Outputs
  • Direct Overriding Load (Data) Inputs
  • Gated Clock Inputs
  • Parallel-to-Serial Data Conversion
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

2 Applications

  • Programable Logic Controllers
  • Appliances
  • Video Display Systems
  • Output Expander
  • Keyboards

3 Description

The SNx4HC165 devices are 8-bit parallel-load shift registers that, when clocked, shift the data toward a serial (QH) output. Parallel-in access to each stage is provided by eight individual direct data (A−H) inputs that are enabled by a low level at the shift/load (SH/LD) input. The SNx4HC165 devices also feature a clock-inhibit (CLK INH) function and a complementary serial (QH) output.

Clocking is accomplished by a low-to-high transition of the clock (CLK) input while SH/LD is held high and CLK INH is held low. The functions of CLK and CLK INH are interchangeable. Because a low CLK and a low-to-high transition of CLK INH also accomplish clocking, CLK INH must be changed to the high level only while CLK is high. Parallel loading is inhibited when SH/LD is held high. While SH/LD is low, the parallel inputs to the register are enabled independently of the levels of the CLK, CLK INH, or serial (SER) inputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74HC165D SOIC (16) 10.00 mm × 6.20 mm
SN74HC165DB SSOP (16) 8.20 mm × 6.50 mm
SN74HC165N PDIP (16) 6.60 mm × 18.92 mm
SN74HC165NS SO (16) 8.20 mm × 9.90 mm
SN74HC165PW TSSOP (16) 6.60 mm × 5.10 mm
SN54HC165FK LCCC (20) 9.09 mm × 9.09 mm
SN54HC165J CDIP (16) 21.34 mm × 7.52 mm
SN54HC165W CFP (16) 9.40 mm × 7.75 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

Logic Diagram Positive Logic

SN54HC165 SN74HC165 Logic.gif