SCLS751 March   2016 SN74HC595B

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Pin Configuration and Functions
  5. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Switching Characteristics
    8. 5.8 Operating Characteristics
    9. 5.9 Typical Characteristics
  6. 6 Parameter Measurement Information
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The SN74HC595B is part of the HC family of logic devices intended for CMOS applications. The SN74HC595B device is an 8-bit shift register that feeds an 8-bit D-type storage register.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both clocks are connected together, the shift register is always one clock pulse ahead of the storage register. The QH' may be used for daisy chaining the device and will not go into high impedance when OE is asserted.

7.2 Functional Block Diagram

SN74HC595B fbd_SCLS751.gif Figure 4. Logic Diagram (Positive Logic)

7.3 Feature Description

The SN74HC595B device is an 8-bit Serial-In, Parallel-Out shift register. It has a wide operating voltage of 2 V to 6 V, and the high-current 3-state outputs can drive up to 15 LSTTL Loads. The device has a low power consumption of 80-μA (Maximum) ICC. Additionally, this device has a low input current of 1 μA (Maximum) and a ±6-mA output drive at 5 V. The device is available currently in the smallest logic QFN package at 0.5 mm max height with 0.4 mm pitch. The inputs are over voltage tolerant independent of Vcc.

7.4 Device Functional Modes

Table 3 lists the functional modes of the SN74HC595B devices.

Table 3. Function Table

INPUTS FUNCTION
SER SRCLK SRCLR RCLK OE
– – – – H Outputs QA – QH are disabled. QH' is active .
– – – – L Outputs QA – QH are enabled.
– – L – – Shift register is cleared.
L ↑ H – – First stage of the shift register goes low.
Other stages store the data of previous stage, respectively.
H ↑ H – – First stage of the shift register goes high.
Other stages store the data of previous stage, respectively.
– – – ↑ – Shift-register data is stored in the storage register.