SCLS737D September   2013  – March 2024 SN74LV1T00

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Related Products
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  8. 7 Parameter Measurement Information
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Clamp Diode Structure
      2. 8.3.2 Balanced CMOS Push-Pull Outputs
      3. 8.3.3 LVxT Enhanced Input Voltage
        1. 8.3.3.1 Down Translation
        2. 8.3.3.2 Up Translation
    4. 8.4 Device Functional Modes
  10. 9 Application and Implementation
    1. 9.1 Power Supply Recommendations
    2. 9.2 Layout
      1. 9.2.1 Layout Guidelines
  11. 10Device and Documentation Support
    1. 10.1 Receiving Notification of Documentation Updates
    2. 10.2 Support Resources
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Parameter Measurement Information

Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω.

For clock inputs, fmax is measured when the input duty cycle is 50%.

The outputs are measured one at a time with one input transition per measurement.

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(1) CL includes probe and test-fixture capacitance.
Figure 7-1 Load Circuit for Push-Pull Outputs
GUID-20200713-CA0I-ZTM5-PTJB-WD0LZ8VNG7PG-low.gif
(1) The greater between tr and tf is the same as tt.
Figure 7-3 Voltage Waveforms, Input and Output Transition Times
GUID-535BFE0F-9D7B-4CA6-85AB-D09CD11F52EA-low.gif
(1) The greater between tPLH and tPHL is the same as tpd.
Figure 7-2 Voltage Waveforms Propagation Delays