Product details

Technology Family LV1T Bits (#) 1 High input voltage (Min) (Vih) 1 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) -8 IOL (Max) (mA) 8
Technology Family LV1T Bits (#) 1 High input voltage (Min) (Vih) 1 High input voltage (Max) (Vih) 5.5 Vout (Min) (V) 1.65 Vout (Max) (V) 5.5 IOH (Max) (mA) -8 IOL (Max) (mA) 8
SOT-23 (DBV) 5 5 mm² 2.9 x 1.6 SOT-SC70 (DCK) 5 4 mm² 2 x 2.1
  • Single-Supply Voltage Translator at 5.0/3.3/2.5/1.8V VCC
  • Operating Range of 1.8V to 5.5V
  • Up Translation
    • 1.2V(1) to 1.8V at 1.8V VCC
    • 1.5V(1) to 2.5V at 2.5V VCC
    • 1.8V(1) to 3.3V at 3.3V VCC
    • 3.3V to 5.0V at 5.0V VCC
  • Down Translation
    • 3.3V to 1.8V at 1.8V VCC
    • 3.3V to 2.5V at 2.5V VCC
    • 5.0V to 3.3V at 3.3V VCC
  • Logic Output is Referenced to VCC
  • Output Drive
    • 8mA Output Drive at 5V
    • 7mA Output Drive at 3.3V
    • 3mA Output Drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm
  • Latch-Up Performance Exceeds 250mA
    Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Supports Standard Logic Pinouts
  • CMOS Output B Compatible with AUP1G and LVC1G Families Refer to the VIH/VIL and output drive for lower VCC condition.
  • Single-Supply Voltage Translator at 5.0/3.3/2.5/1.8V VCC
  • Operating Range of 1.8V to 5.5V
  • Up Translation
    • 1.2V(1) to 1.8V at 1.8V VCC
    • 1.5V(1) to 2.5V at 2.5V VCC
    • 1.8V(1) to 3.3V at 3.3V VCC
    • 3.3V to 5.0V at 5.0V VCC
  • Down Translation
    • 3.3V to 1.8V at 1.8V VCC
    • 3.3V to 2.5V at 2.5V VCC
    • 5.0V to 3.3V at 3.3V VCC
  • Logic Output is Referenced to VCC
  • Output Drive
    • 8mA Output Drive at 5V
    • 7mA Output Drive at 3.3V
    • 3mA Output Drive at 1.8V
  • Characterized up to 50MHz at 3.3V VCC
  • 5V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (DCK)
    • 2 × 2.1 × 0.65 mm
  • Latch-Up Performance Exceeds 250mA
    Per JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model
      (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Supports Standard Logic Pinouts
  • CMOS Output B Compatible with AUP1G and LVC1G Families Refer to the VIH/VIL and output drive for lower VCC condition.

SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors.

The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

SN74LV1T00 is a low voltage CMOS gate logic that operates at a wider voltage range for industrial, portable, telecom, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8V/2.5V/3.3V/5V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8V input logic at VCC = 3.3V and can be used in 1.8V to 3.3V level up translation. In addition, the 5V tolerant input pins enable down translation (e.g. 3.3V to 2.5V output at VCC = 2.5V). The wide VCC range of 1.8V to 5.5V allows generation of desired output levels to connect to controllers or processors.

The SN74LV1T00 is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

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Technical documentation

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Type Title Date
* Data sheet Single Power Supply 2-INPUT POSITIVE NAND GATE CMOS Logic Level Shifter datasheet (Rev. B) 21 Feb 2014
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
Application note LV1T Family of single supply translators (Rev. A) 29 Dec 2014
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
In stock
Limit: 5
Simulation model

SN74LV1T00 IBIS Model (Rev. A)

SCLM103A.ZIP (43 KB) - IBIS Model
Simulation model

SN74LV1T00 Behavioral SPICE Model

SCLM187.ZIP (7 KB) - PSpice Model
Reference designs

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Reference designs

TIDA-01041 — Battery tester reference design for multi-phase high-precision 0.5 to 100 A battery formation

This reference design provides a multi-phase solution for a wide range of current battery test applications. Leveraging the dual phase buck/boost controller LM5170's daisy chain configuration gives the design the ability to achieve 100A charging/discharging rates. Utilizing high accuracy constant (...)
Reference designs

TIDA-01042 — Modular battery tester reference design for 50-A, 100-A, and 200-A applications

This reference design provides a modular battery test solution allowing users to have the flexibility to test batteries at different current levels with one design. This design leverages the TIDA-01041 reference design by providing two 100-A battery testers that can work independently or be (...)
Package Pins Download
SC70 (DCK) 5 View options
SOT-23 (DBV) 5 View options

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