SCLS427J April 1999 – February 2024 SN74LV4066A
PRODUCTION DATA
- 1
- 1 Features
- 2 Applications
- 3 Description
- 4 Pin Configuration and Functions
-
5 Specifications
- 5.1 Absolute Maximum Ratings
- 5.2 ESD Ratings
- 5.3 Thermal Information: SN74LV4066A
- 5.4 Recommended Operating Conditions
- 5.5 Electrical Characteristics (LV)
- 5.6 Timing Characteristics VCC = 2.5V ± 0.2V
- 5.7 Timing Characteristics VCC = 3.3V ± 0.3V
- 5.8 Timing Characteristics VCC = 5V ± 0.5V
- 5.9 AC Characteristics
- 6 Parameter Measurement Information
- 7 Detailed Description
- 8 Device and Documentation Support
- 9 Revision History
- 10Mechanical, Packaging, and Orderable Information
Package Options
Refer to the PDF data sheet for device specific package drawings
Mechanical Data (Package|Pins)
- D|14
- RGY|14
- DB|14
- DGV|14
- PW|14
- N|14
- NS|14
Thermal pad, mechanical data (Package|Pins)
Orderable Information
3 Description
This quadruple silicon-gate CMOS analog switch is designed for 1.65V to 5.5V VCC operation.
These switches are designed to handle both analog and digital signals. Each switch permits signals with amplitudes up to 5.5V (peak) to be transmitted in either direction.
Each switch section has its own enable-input control (C). A high-level voltage applied to C turns on the associated switch section.
Applications include signal gating, chopping, modulation or demodulation (modem), and signal multiplexing for analog-to-digital and digital-to-analog conversion systems.
Package Information
| PART NUMBER | PACKAGE(1) | PACKAGE SIZE(2) |
|---|---|---|
| SN74LV4066A | D (SOIC, 14) | 8.65mm × 6mm |
| PW (TSSOP, 14) | 5mm × 6.4mm | |
| RGY (QFN, 14) | 3.5mm × 3.5mm |
(1) For more information, see Section 10.
(2) The package size (length × width) is a nominal value and includes
pins, where applicable.
Logic Diagram (Positive Logic)