SCLS749B February   2014  – September 2014 SN74LV4T125

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Application Diagram
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Noise Characteristics
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Translating Down
      2. 9.1.2 Translating Up
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Additional Product Selection
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Single-Supply Voltage Translator at
    5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Supports Standard Logic Pinouts
  • CMOS Output B Compatible with AUP125, LVC125 (1)
(1) Refer the VIH/VIL and output drive for lower VCC condition.

2 Applications

  • Tablet
  • Smartphone
  • Personal Computer
  • Industrial Automotive

3 Description

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
SN74LV4T125 TSSOP (14) 5.00 mm x 4.40 mm
VQFN (14) 3.50 mm x 3.50 mm
  1. For all available packages, see the orderable addendum at the end of the data sheet.

4 Simplified Application Diagram

simp_1pg_SCLS749.gif