SN74LV4T125 Single Power Supply Quadruple Buffer GATE w/ 3-State Output CMOS Logic Level Shifter | TI.com

SN74LV4T125 (ACTIVE) Single Power Supply Quadruple Buffer GATE w/ 3-State Output CMOS Logic Level Shifter

Single Power Supply Quadruple Buffer GATE w/ 3-State Output CMOS Logic Level Shifter - SN74LV4T125
Datasheet
SN74LV4T125 Single Power Supply Quadruple Buffer Translator GATE With 3-State Output CMOS Logic Level Shifter datasheet (Rev. B)
 

Description

SN74LV4T125 is a low-voltage CMOS buffer gate that operates at a wider voltage range for portable, telecom, industrial, and automotive applications. The output level is referenced to the supply voltage and is able to support 1.8-V, 2.5-V, 3.3-V, and 5-V CMOS levels.

The input is designed with a lower threshold circuit to match 1.8-V input logic at VCC = 3.3 V and can be used in 1.8 V to 3.3 V level-up translation. In addition, the 5-V tolerant input pins enable down translation (for example, 3.3 V to 2.5 V output at VCC = 2.5 V). The wide VCC range of 1.8 V to 5.5 V allows the generation of desired output levels to connect to controllers or processors.

The SN74LV4T125 device is designed with current-drive capability of 8 mA to reduce line reflections, overshoot, and undershoot caused by high-drive outputs.

Features

  • Single-Supply Voltage Translator at
    5.0-V, 3.3-V, 2.5-V, and 1.8-V VCC
  • Operating Range of 1.8 V to 5.5 V
  • Up Translation
    • 1.2 V(1) to 1.8 V at 1.8-V VCC
    • 1.5 V(1) to 2.5 V at 2.5-V VCC
    • 1.8 V(1) to 3.3 V at 3.3-V VCC
    • 3.3 V to 5.0 V at 5.0-V VCC
  • Down Translation
    • 3.3 V to 1.8 V at 1.8-V VCC
    • 3.3 V to 2.5 V at 2.5-V VCC
    • 5.0 V to 3.3 V at 3.3-V VCC
  • Logic Output is Referenced to VCC
  • Characterized up to 50 MHz at 3.3-V VCC
  • 5.5 V Tolerance on Input Pins
  • –40°C to 125°C Operating Temperature Range
  • Pb-Free Packages Available: SC-70 (RGY)
    • 3.5 × 3.5 × 1 mm
  • Latch-Up Performance Exceeds 250 mA Per
    JESD 17
  • ESD Performance Tested Per JESD 22
    • 2000-V Human-Body Model (A114-B, Class II)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Supports Standard Logic Pinouts
  • CMOS Output B Compatible with AUP125, LVC125 Refer the VIH/VIL and output drive for lower VCC condition.

Parametrics

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Part number Order Technology Family Bits (#) Voltage (Nom) (V) IOH (Max) (mA) IOL (Max) (mA) F @ nom voltage (Max) (MHz) ICC @ nom voltage (Max) (mA) Schmitt trigger tpd @ nom Voltage (Max) (ns) Rating Operating temperature range (C) Package Group
SN74LV4T125 Order now LV-A     4     1.8
2.5
3.3
5    		 -16     16     50     0.02     No     12
7
5.5
3.5    		 Catalog     -40 to 125     TSSOP | 14
VQFN | 14    
SN74LV1T125 Order now LV1T     1     1.8
2.5
3.3
5.5    		 -8     8     50     0.01     No     14.5
9.5
8.0
6.5    		 Catalog     -40 to 125     SC70 | 5
SOT-23 | 5    
SN74LV1T126 Order now LV1T     1     1.8
2.5
3.3
5.5    		 -8     8     50     0.01     No     14.5
9.5
8.0
6.5    		 Catalog     -40 to 125     SC70 | 5
SOT-23 | 5    
SN74LV1T34 Order now LV1T     1     1.8
2.5
3.3
5.5    		 -8     8     50     0.01     No     14.5
9.5
8.0
6.5    		 Catalog     -40 to 125     SC70 | 5
SOT-23 | 5