SCAS699C August   2003  – June 2014 SN74LVC16244A

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Simplified Schematic
  5. Revision History
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics—DC Limit Changes
    6. 7.6 Switching Characteristics, -40°C to 85°C
    7. 7.7 Switching Characteristics, -40°C to 125°C
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGG|48
  • DL|48
  • DGV|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Application and Implementation

10.1 Application Information

The SN74LVC16244A device is a 16-bit buffer/driver. This device can be used as four 4-bit, two 8-bit, or one 16-bit buffer. It allows data transmission from the A bus to the Y bus with 4 separate enable pins that control 4 bits each. The output-enable (OE) input can be used to disable sections of the device so that the buses are effectively isolated. The device has 5.5 V tolerant inputs at any valid VCC which allows it to be used in multi-power systems and can be used for down translation.

10.2 Typical Application

app_sche_cas699.gifFigure 4. Typical Application Diagram

10.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads; therefore, routing and load conditions should be considered to prevent ringing.

10.2.2 Detailed Design Procedure

  1. Recommended Input Conditions
  2. Recommend Output Conditions
    • Load currents should not exceed 25 mA per output and 50 mA total for the part.
    • Outputs should not be pulled above VCC.

10.2.3 Application Curves

D003_SCES062.gifFigure 5. ICC vs Frequency