SCAS755B December   2003  – June 2014 SN74LVC16373A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Simplified Schematic
  5. 5 Revision History
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Operating Characteristics
    9. 7.9 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Trademarks
    2. 13.2 Electrostatic Discharge Caution
    3. 13.3 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DGG|48
  • DL|48
  • DGV|48
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Pin Configuration and Functions

po_dgg_cas755.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 OE I Output Enable
2 1Q1 O 1Q1 Output
3 1Q2 O 1Q2 Output
4 GND — Ground Pin
5 1Q3 O 1Q3 Output
6 1Q4 O 1Q4 Output
7 VCC — Power Pin
8 1Q5 O 1Q5 Output
9 1Q6 O 1Q6 Output
10 GND — Ground Pin
11 1Q7 O 1Q7 Output
12 1Q8 O 1Q8 Output
13 2Q1 O 2Q1 Output
14 2Q2 O 2Q2 Output
15 GND — Ground Pin
16 2Q3 O 2Q3 Output
17 2Q4 O 2Q4 Output
18 VCC — Power Pin
19 2Q5 O 2Q5 Output
20 2Q6 O 2Q6 Output
21 GND — Ground Pin
22 2Q7 O 2Q7 Output
23 2Q8 O 2Q8 Output
24 2OE O Output Enable 2
25 2LE I Latch Enable 2
26 2D8 I 2D8 Input
27 2D7 I 2D7 Input
28 GND — Ground Pin
29 2D6 I 2D6 Input
30 2D5 I 2D5 Input
31 VCC — Power Pin
32 2D4 I 2D4 Input
33 2D3 I 2D3 Input
34 GND — Ground Pin
35 2D2 I 2D2 Input
36 2D1 I 2D1 Input
37 1D8 I 1D8 Input
38 1D7 I 1D7 Input
39 GND — Ground Pin
40 1D6 I 1D6 Input
41 1D5 I 1D5 Input
42 VCC — Power Pin
43 1D4 I 1D4 Input
44 1D3 I 1D3 Input
45 GND — Ground Pin
46 1D2 I 1D2 Input
47 1D1 I 1D1 Input
48 1LE I Latch Enable 1
po2_cas755.gif

Pin Assignments(1) (56-Ball GQL or ZQL Package)

1 2 3 4 5 6
A 1OE NC NC NC NC 1LE
B 1Q2 1Q1 GND GND 1D1 1D2
C 1Q4 1Q3 VCC VCC 1D3 1D4
D 1Q6 1Q5 GND GND 1D5 1D6
E 1Q8 1Q7 1D7 1D8
F 2Q1 2Q2 2D2 2D1
G 2Q3 2Q4 GND GND 2D4 2D3
H 2Q5 2Q6 VCC VCC 2D6 2D5
J 2Q7 2Q8 GND GND 2D8 2D7
K 2OE NC NC NC NC 2LE
(1) NC – No internal connection
po3_cas755.gif

Pin Assignments(1) (54-Ball GRD or ZRD Package)

1 2 3 4 5 6
A 1Q1 NC 1OE 1LE NC 1D1
B 1Q3 1Q2 NC NC 1D2 1D3
C 1Q5 1Q4 VCC VCC 1D4 1D5
D 1Q7 1Q6 GND GND 1D6 1D7
E 2Q1 1Q8 GND GND 1D8 2D1
F 2Q3 2Q2 GND GND 2D2 2D3
G 2Q5 2Q4 VCC VCC 2D4 2D5
H 2Q7 2Q6 NC NC 2D6 2D7
J 2Q8 NC 2OE 2LE NC 2D8
(1) NC – No internal connection