SCES602E August   2004  – January 2018 SN74LVC1G139

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specification
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Switching Characteristics
    7. 6.7 Operating Characteristics
  7. 7 Typical Characteristics
  8. 8 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
    4. 9.4 Device Functional Modes
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Documentation Support
      1. 13.1.1 Related Documentation
    2. 13.2 Community Resources
    3. 13.3 Trademarks
    4. 13.4 Electrostatic Discharge Caution
    5. 13.5 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Parameter Measurement Information

Unless otherwise noted, all input pulses are supplied by generators that have the following characteristics:

  • PRR ≤ 10 MHz
  • ZO = 50 Ω

NOTE

All parameters and waveforms are not applicable to all devices.

SN74LVC1G139 sces602_load_circuit.gif
1. CL includes probe and jig capacitance.
Figure 2. Load Circuit

Table 1. Loading Conditions for Parameter

TEST S1
tPLH(3), tPHL(3) Open
tPLZ(1), tPZL(2) VLOAD
tPHZ(1), tPZH(2) GND
(1) tPLZ and tPHZ are the same as tdis.
(2) tPZL and tPZH are the same as ten.
(3) tPLH and tPHL are the same as tpd.

Table 2. Loading Conditions for VCC – Case 1

VCC INPUTSVMVLOAD CL RL VΔ
VItr/tf
1.8 V ± 0.15 V VCC ≤ 2 ns VCC / 2 2 × VCC 15 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤ 2 ns VCC / 2 2 × VCC 15 pF 1 MΩ 0.15 V
3.3 V ± 0.3 V 3 V ≤ 2.5 ns 1.5 V 6 V 15 pF 1 MΩ 0.3 V
5 V ± 0.5 V VCC ≤ 2.5 ns VCC / 2 2 × VCC 15 pF 1 MΩ 0.3 V

Table 3. Loading Conditions for VCC – Case 2

VCC INPUTSVMVLOAD CL RL VΔ
VItr/tf
1.8 V ± 0.15 V VCC ≤ 2 ns VCC / 2 2 × VCC 30 pF 1 MΩ 0.15 V
2.5 V ± 0.2 V VCC ≤ 2 ns VCC / 2 2 × VCC 30 pF 500 MΩ 0.15 V
3.3 V ± 0.3 V 3 V ≤ 2.5 ns 1.5 V 6 V 30 pF 500 MΩ 0.3 V
5 V ± 0.5 V VCC ≤ 2.5 ns VCC / 2 2 × VCC 30 pF 500 MΩ 0.3 V
SN74LVC1G139 sces602_voltage_waveforms_pulse_duration.gifFigure 3. Voltage Waveforms: Pulse Duration
SN74LVC1G139 sces602_voltage_waveforms_propagation_delay_times_inverting_and_non_inverting_outputs.gif
1. The outputs are measured one at a time, with one transition per measurement.
Figure 4. Voltage Waveforms: Propagation Delay Times Inverting And Noninverting Outputs
SN74LVC1G139 sces602_voltage_waveforms_setup_and_hold_times.gifFigure 5. Voltage Waveforms: Setup and Hold Times
SN74LVC1G139 sces602_voltage_waveforms_enable_and_disable_times_low_and_high_level_enabling.gif
1. Waveform 1 is for an output with internal conditions such that the output is low, except when disabled by the output control.
2. Waveform 2 is for an output with internal conditions such that the output is high, except when disabled by the output control.
3. The outputs are measured one at a time, with one transition per measurement.
Figure 6. Voltage Waveforms: Enable and Disable Times, Low- and High-Level Enabling