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SN74LVC1G139

ACTIVE

2-Line-to-4-Line Decoder

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Data sheet

SN74LVC1G139

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 85 Rating Catalog Supply current (max) (µA) 10
Technology family LVC Number of channels 1 Operating temperature range (°C) -40 to 85 Rating Catalog Supply current (max) (µA) 10
SSOP (DCT) 8 11.8 mm² (2.95 mm × 4 mm) VSSOP (DCU) 8 6.2 mm² (2 mm × 3.1 mm) DSBGA (YZP) 8 2.8125 mm² (— mm × — mm)
  • Available in the Texas Instruments
    NanoStar™ and NanoFree™ Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 4.9 ns at 3.3 V and 15 pF
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments
    NanoStar™ and NanoFree™ Packages
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Maximum tpd of 4.9 ns at 3.3 V and 15 pF
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This SN74LVC1G139 2-to-4 line decoder is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

This SN74LVC1G139 2-to-4 line decoder is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G139 2-line to 4-line decoder is designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When used with high-speed memories using a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

NanoStar and NanoFree package technology is a major breakthrough in device packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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Technical documentation

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* Data sheet SN74LVC1G139 2-to-4 Line Decoder datasheet (Rev. E) PDF | HTML Jan 9, 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Simulation model

SN74LVC1G139 IBIS Model (Rev. A)

SCEM449 (245 KB) - IBIS model
Supported products & hardware
Reference design

TIDA-01565 — Wired-OR MUX and PGA Reference Design

This board demonstrates a wired-OR multiplexer (MUX) and a programmable gain amplifier (PGA) application of the OPA837 operational amplifier. These applications are made possible with the high-impedance output of the amplifier and the high-impedance inverting input while in power-down (PD) mode. It (...)
Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SSOP (DCT) 8 Ultra Librarian
VSSOP (DCU) 8 Ultra Librarian
DSBGA (YZP) 8 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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