SCES560G March 2004 – June 2015 SN74LVC1G175
This single D-type flip-flop is designed for 1.65-V to 5.5-V VCC operation.
The SN74LVC1G175 device has an asynchronous clear (CLR) input. When CLR is high, data from the input pin (D) is transferred to the output pin (Q) on the clock's (CLK) rising edge. When CLR is low, Q is forced into the low state, regardless of the clock edge or data on D.
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This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
The SN74LVC1G175 device has a wide operating VCC range of 1.65 V to 5.5 V, which allows it to be used in a broad range of systems. The 5.5-V I/Os allow down translation and also allow voltages at the inputs when
VCC = 0.
Table 1 lists the functional modes for SN74LVC1G175.
|H||H or L||X||Q0|