SCES874 March 2017 SN74LVC1G79-Q1
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
A useful application for the SN74LVC1G79-Q1 is using it as a data latch with low-voltage data retention. This application implements the use of a microcontroller GPIO pin to act as a clock to set the output state and a second GPIO to provide the input data. If the SN74LVC1G79-Q1 is being powered from 1.8V and there is concern that a power glitch could exist as low as 1.5V, the device will retain the state of the Q output. An example of this data retention is shown in Figure 8 where the VCC drops to 1.5V and the Q output maintains the HIGH output state when VCC returns to 1.8V. If the VCC voltage drops below 1.5V, data retention is not guaranteed.
The SN74LVC1G79-Q1 device uses CMOS technology and has balanced output drive. Take care to avoid bus contention because it can drive currents that would exceed maximum limits.