SCES220U April   1999  – April 2017 SN74LVC1G79

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: TA = -40°C to +85°C
    7. 6.7  Timing Requirements: TA = -40°C to +125°C
    8. 6.8  Switching Characteristics: CL = 15 pF, TA = -40°C to +85°C
    9. 6.9  Switching Characteristics: CL = 30 or 50 pF, TA = -40°C to +85°C
    10. 6.10 Switching Characteristics: CL = 30 pF or 50 pF, TA = -40°C to +125°C
    11. 6.11 Operating Characteristics
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Balanced High-Drive CMOS Push-Pull Outputs
      2. 8.3.2 Standard CMOS Inputs
      3. 8.3.3 Clamp Diodes
      4. 8.3.4 Partial Power Down (Ioff)
      5. 8.3.5 Over-Voltage Tolerant Inputs
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Receiving Notification of Documentation Updates
    3. 12.3 Community Resources
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • DBV|5
  • DCK|5
  • DRL|5
  • YZP|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5 Pin Configuration and Functions

DBV Package
5-Pin SOT-23
Top View
SN74LVC1G79 sn74lvc1g79-sn74lvc1g79-po-2-ces220-01-pinout.gif
DCK Package
5-Pin SC70
Top View
SN74LVC1G79 sn74lvc1g79-sn74lvc1g79-po-2-ces220-02-pinout.gif
See mechanical drawings for dimensions.
DRL Package
5-Pin SOT
Top View
SN74LVC1G79 SN74LVC1G79Pinout-DCK.gif
YZP Package
5-Pin DSBGA
Bottom View
SN74LVC1G79 YZP_bga_pin_diagram.gif

Pin Functions

PIN I/O DESCRIPTION
NAME DBV, DCK, DRL YZP
D 1 A1 I Data input
CLK 2 B1 I Positive-Edge-Triggered Clock input
GND 3 C1 — Ground
Q 4 C2 O Non-inverted output
VCC 5 A2 — Positive Supply