SCAS757B December   2003  – September 2014 SN74LVCH16374A

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Simplified Schematic
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Handling Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Operating Characteristics
    9. 6.9 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Trademarks
    2. 11.2 Electrostatic Discharge Caution
    3. 11.3 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The SN74LVCH16374A device is a high-drive CMOS device that can be used for a multitude of bus-interface type applications where the data needs to be retained or latched. The SN74LVCH16374A device can produce 24 mA of drive current at 3.3 V; thus, making it ideal for driving multiple outputs and appropriate for high-speed applications up to 150 MHz. The inputs are 5.5-V tolerant allowing it to translate down to VCC. The Ioff feature allows voltages on the inputs and outputs when VCC is 0 V. The Bus Hold feature eliminates the need for external pull-up or pull-down resistors on unused or floating inputs.

8.2 Typical Application

app_sche_cas757.gifFigure 5. Typical Application Schematic

8.2.1 Design Requirements

This device uses CMOS technology and has balanced output drive. Care should be taken to avoid bus contention because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into light loads, so routing and load conditions should be considered to prevent ringing.

8.2.2 Detailed Design Procedure

  1. Recommended input conditions
  2. Recommend output conditions
    • Load currents should not exceed 50 mA per output and 100 mA total for the part.
    • Outputs should not be pulled above VCC.

8.2.3 Application Curves

D003_SCAS757.gifFigure 6. ICC vs Frequency