SLLSEW8 September   2016 SN75LVPE801


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1  SATA Express
      2. 9.3.2  Receiver Termination
      3. 9.3.3  Receiver Internal Bias
      4. 9.3.4  Receiver Equalization
      5. 9.3.5  OOB/Squelch
      6. 9.3.6  Auto Low Power
      7. 9.3.7  Transmitter Output Signal
      8. 9.3.8  Transmitter Common Mode
      9. 9.3.9  De-Emphasis
      10. 9.3.10 Transmitter Termination
    4. 9.4 Device Functional Modes
      1. 9.4.1 Active
      2. 9.4.2 Squelch
      3. 9.4.3 Auto Low Power
  10. 10Applications and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical SATA Applications
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
      4. 10.2.4 SATA Express Applications
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Curve
      5. 10.2.5 PCIe Applications
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 Return Current and Plane References
      2. 12.1.2 Split Planes - What to Avoid
      3. 12.1.3 Avoiding Crosstalk
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

12 Layout

12.1 Layout Guidelines

12.1.1 Return Current and Plane References

High frequency return signal/current is defined as the path that a signal follows back to its original source as all signals flow in a closed loop. Minimizing the loop area of the closed loop is beneficial for both EMI (Electro-Magnetic Interference) reduction and signal integrity.

The best way to minimize loop area is to always have a signal reference their nearest solid ground or power plane. Obstructions to the return signal causes signal integrity problems like reflections, crosstalk, undershoot and overshoot.

Signals can reference either power or ground planes, but ground is preferred. Without solid plane references, single ended and differential impedance control is very hard to accomplish; crosstalk to other signals may happen as the return signals have no other path. This type of crosstalk is difficult to troubleshoot.

Symmetric pairing of solid planes in the layer stackup can significantly reduce warping of the PCB during the manufacturing process. Warping of the PCB is crucial to minimize on boards that uses BGA components.

12.1.2 Split Planes – What to Avoid

Never route signals over splits in their perspective reference planes.

SN75LVPE801 ovrlapping_planes_llu149.gif Figure 28. Overlapping Analog and Digital Planes
SN75LVPE801 incorrect_routing_llu149.gif Figure 29. Incorrect Routing
SN75LVPE801 proper_routing_llu149.gif Figure 30. Proper Routing

12.1.3 Avoiding Crosstalk

Crosstalk is defined as interference from one trace to another by either or both inductive and capacitive coupling. Best ways to avoid crosstalk are:

  • Provide stable reference planes for all high speed signals (as noted in previous sections).
  • Use the 3W rule (3 times the width of trace for separation) where applicable on all signals, but absolutely use on clock signals.
  • Use ground traces/guards around either victim or aggressor signals prone to crosstalk.
  • When space is constrained and limited on areas of the PCB to route parallel buses, series or end termination resistors can be used to route traces closer than what is normally recommended. However, calculations and simulations must be done to validate the use of series or end termination resistors to eliminate crosstalk.
SN75LVPE801 avoid_crosstalk_llu149.gif Figure 31. Ways to Avoid Crosstalk

12.2 Layout Example

SN75LVPE801 nom_pcb_stackup_llu149.gif Figure 32. Printed-Circuit Board Stackup (FR-4 Example)
SN75LVPE801 pcb_layout_suggestions_llu149.gif
PCB layer configuration suggestions for stackup symmetry and signal integrity.
Figure 33. PCB Layer Configuration Suggestions