SLLSET1B January   2016  – February 2017 SN75LVPE802

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Switching Characteristics
    8. 7.8 Typical Characteristics
      1. 7.8.1 Jitter and VOD results: Case 1 at 6 Gbps
      2. 7.8.2 Jitter and VOD Results: Case 2 at 3 Gbps
      3. 7.8.3 Jitter and VOD Results: Case 3 at 1.5 Gbps
      4. 7.8.4 Jitter and VOD Results: Case 4 at 8 Gbps
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  SATA Express
      2. 8.3.2  Receiver Termination
      3. 8.3.3  Receiver Internal Bias
      4. 8.3.4  Input Equalization
      5. 8.3.5  OOB/Squelch
      6. 8.3.6  Auto Low Power
      7. 8.3.7  Transmitter Output Signal
      8. 8.3.8  Transmitter Common Mode
      9. 8.3.9  De-Emphasis
      10. 8.3.10 Transmitter Termination
    4. 8.4 Device Functional Modes
      1. 8.4.1 Low-Power Mode
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical SATA Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Equalization Configuration
      3. 9.2.3 De-emphasis Configuration
      4. 9.2.4 Application Curves
        1. 9.2.4.1 SN75LVPE802 Equalization Settings for Various Input Trace Length
        2. 9.2.4.2 SN75LVCP802 De-emphasis Settings For various Output Trace Lengths
    3. 9.3 SATA Express Applications
      1. 9.3.1 Detailed Design Procedure
      2. 9.3.2 PCIe Applications
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Receiving Notification of Documentation Updates
    2. 12.2 Community Resources
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • RTJ|20
Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Revision History

Changes from A Revision (September 2016) to B Revision

  • Changed Figure 27 note From: Input Trace Length = 53 in. To: Input Trace Length = 3 in.Go
  • Changed title of Figure 35 From: Output Eye (TP2) to: Input Eye (TP2) Go
  • Changed Figure 37 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. Go
  • Changed Figure 38 note From: Input Trace Length = 36 in. To: Input Trace Length = 48 in. Go
  • Changed title of Figure 38 From: Input Eye (TP4) To: Output Eye (TP4)Go
  • Changed note in Figure 40 From: Output Trace Length = 0 in To: Output Trace Length = 3 in.Go
  • Changed note in Figure 42 From: Output Trace Length = 6 in To: Output Trace Length = 12 in.Go

Changes from * Revision (January 2016) to A Revision

  • Changed the device From: Product Preview To: Production Go