SLASF37A January   2024  – January 2025 TAA5412-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Timing Requirements: I2C Interface
    7. 5.7  Switching Characteristics: I2C Interface
    8. 5.8  Timing Requirements: SPI Interface
    9. 5.9  Switching Characteristics: SPI Interface
    10. 5.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 5.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 5.12 Timing Requirements: PDM Digital Microphone Interface
    13. 5.13 Switching Characteristics: PDM Digial Microphone Interface
    14. 5.14 Timing Diagrams
    15. 5.15 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1  Serial Interfaces
        1. 6.3.1.1 Control Serial Interfaces
        2. 6.3.1.2 Audio Serial Interfaces
          1. 6.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 6.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 6.3.1.2.3 Left-Justified (LJ) Interface
        3. 6.3.1.3 Using Multiple Devices With Shared Buses
      2. 6.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 6.3.3  Input Channel Configuration
      4. 6.3.4  Reference Voltage
      5. 6.3.5  Microphone Bias
      6. 6.3.6  Digital PDM Microphone Record Channel
      7. 6.3.7  Signal-Chain Processing
        1. 6.3.7.1 ADC Signal-Chain
          1. 6.3.7.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 6.3.7.1.2  Programmable Channel Gain and Digital Volume Control
          3. 6.3.7.1.3  Programmable Channel Gain Calibration
          4. 6.3.7.1.4  Programmable Channel Phase Calibration
          5. 6.3.7.1.5  Programmable Digital High-Pass Filter
          6. 6.3.7.1.6  Programmable Digital Biquad Filters
          7. 6.3.7.1.7  Programmable Channel Summer and Digital Mixer
          8. 6.3.7.1.8  Configurable Digital Decimation Filters
            1. 6.3.7.1.8.1 Linear-phase filters
              1. 6.3.7.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 6.3.7.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 6.3.7.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 6.3.7.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 6.3.7.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 6.3.7.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 6.3.7.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 6.3.7.1.8.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 6.3.7.1.8.1.9 Sampling Rate: 768kHz or 705.6kHz
            2. 6.3.7.1.8.2 Low-latency Filters
              1. 6.3.7.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 6.3.7.1.8.3 Ultra-Low-Latency Filters
              1. 6.3.7.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 6.3.7.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 6.3.7.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 6.3.7.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 6.3.7.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 6.3.7.1.9  Automatic Gain Controller (AGC)
          10. 6.3.7.1.10 Voice Activity Detection (VAD)
          11. 6.3.7.1.11 Ultrasonic Activity Detection (UAD)
      8. 6.3.8  Interrupts, Status, and Digital I/O Pin Multiplexing
      9. 6.3.9  Input DC Fault Diagnostics
      10. 6.3.10 Power Tune Mode
    4. 6.4 Device Functional Modes
      1. 6.4.1 Sleep Mode or Software Shutdown
      2. 6.4.2 Software Reset
      3. 6.4.3 Active Mode
    5. 6.5 Programming
      1. 6.5.1 Control Serial Interfaces
        1. 6.5.1.1 I2C Control Interface
          1. 6.5.1.1.1 General I2C Operation
          2. 6.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 6.5.1.1.2.1 I2C Single-Byte Write
            2. 6.5.1.1.2.2 I2C Multiple-Byte Write
            3. 6.5.1.1.2.3 I2C Single-Byte Read
            4. 6.5.1.1.2.4 I2C Multiple-Byte Read
        2. 6.5.1.2 SPI Control Interface
  8. 7 Register Maps
    1. 7.1 Device Configuration Registers
      1. 7.1.1 TAA5412-Q1_B0_P0 Registers
      2. 7.1.2 TAA5412-Q1_B0_P1 Registers
      3. 7.1.3 TAA5412-Q1_B0_P3 Registers
    2. 7.2 Programmable Coefficient Registers
      1. 7.2.1 Programmable Coefficient Registers: Page 8
      2. 7.2.2 Programmable Coefficient Registers: Page 9
      3. 7.2.3 Programmable Coefficient Registers: Page 10
      4. 7.2.4 Programmable Coefficient Registers: Page 11
      5. 7.2.5 Programmable Coefficient Registers: Page 19
      6. 7.2.6 Programmable Coefficient Registers: Page 27
      7. 7.2.7 Programmable Coefficient Registers: Page 28
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Application
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
      4. 8.2.4 Application Performance Plots
      5. 8.2.5 Example Device Register Configuration Scripts for EVM Setup
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.3 Programmable Coefficient Registers: Page 10

This register page shown in Table 7-184 consists of the prorammable coefficients for the mixer 1 to 4 and and first-order IIR filter. All channel mixer coefficients are 32-bit, two’s complement numbers using a 1.31 number format. The value of 0x7FFFFFFF is equivalent to +1 (0-dB gain), the value 0x00000000 is equivalent to mute (zero data) and all values in between set the mixer attenuation computed accordingly (hex2dec(value)/231). If the MSB is set to '1' then the attenuation remains the same but the signal phase is inverted.

Table 7-180 Page 10 Programmable Coefficient Registers
ADDRESS REGISTER RESET DESCRIPTION
0x00 PAGE[7:0] 0x00 Device Page Register
0x08 ADC_MIX1_CH1_BYT1[7:0] 0x7F Digital mixer 1, ADC channel 1 coefficient byte[31:24]
0x09 ADC_MIX1_CH1_BYT2[7:0] 0xFF Digital mixer 1, ADC channel 1 coefficient byte[23:16]
0x0A ADC_MIX1_CH1_BYT3[7:0] 0xFF Digital mixer 1, ADC channel 1 coefficient byte[15:8]
0x0B ADC_MIX1_CH1_BYT4[7:0] 0xFF Digital mixer 1, ADC channel 1 coefficient byte[7:0]
0x0C ADC_MIX1_CH2_BYT1[7:0] 0x00 Digital mixer 1, ADC channel 2 coefficient byte[31:24]
0x0D ADC_MIX1_CH2_BYT2[7:0] 0x00 Digital mixer 1, ADC channel 2 coefficient byte[23:16]
0x0E ADC_MIX1_CH2_BYT3[7:0] 0x00 Digital mixer 1, ADC channel 2 coefficient byte[15:8]
0x0F ADC_MIX1_CH2_BYT4[7:0] 0x00 Digital mixer 1, ADC channel 2 coefficient byte[7:0]
0x10 ADC_MIX1_CH3_BYT1[7:0] 0x00 Digital mixer 1, ADC channel 3 coefficient byte[31:24]
0x11 ADC_MIX1_CH3_BYT2[7:0] 0x00 Digital mixer 1, ADC channel 3 coefficient byte[23:16]
0x12 ADC_MIX1_CH3_BYT3[7:0] 0x00 Digital mixer 1, ADC channel 3 coefficient byte[15:8]
0x13 ADC_MIX1_CH3_BYT4[7:0] 0x00 Digital mixer 1, ADC channel 3 coefficient byte[7:0]
0x14 ADC_MIX1_CH4_BYT1[7:0] 0x00 Digital mixer 1, ADC channel 4 coefficient byte[31:24]
0x15 ADC_MIX1_CH4_BYT2[7:0] 0x00 Digital mixer 1, ADC channel 4 coefficient byte[23:16]
0x16 ADC_MIX1_CH4_BYT3[7:0] 0x00 Digital mixer 1, ADC channel 4 coefficient byte[15:8]
0x17 ADC_MIX1_CH4_BYT4[7:0] 0x00 Digital mixer 1, ADC channel 4 coefficient byte[7:0]
0x18 ADC_MIX2_CH1_BYT1[7:0] 0x00 Digital mixer 2, ADC channel 1 coefficient byte[31:24]
0x19 ADC_MIX2_CH1_BYT2[7:0] 0x00 Digital mixer 2, ADC channel 1 coefficient byte[23:16]
0x1A ADC_MIX2_CH1_BYT3[7:0] 0x00 Digital mixer 2, ADC channel 1 coefficient byte[15:8]
0x1B ADC_MIX2_CH1_BYT4[7:0] 0x00 Digital mixer 2, ADC channel 1 coefficient byte[7:0]
0x1C ADC_MIX2_CH2_BYT1[7:0] 0x7F Digital mixer 2, ADC channel 2 coefficient byte[31:24]
0x1D ADC_MIX2_CH2_BYT2[7:0] 0xFF Digital mixer 2, ADC channel 2 coefficient byte[23:16]
0x1E ADC_MIX2_CH2_BYT3[7:0] 0xFF Digital mixer 2, ADC channel 2 coefficient byte[15:8]
0x1F ADC_MIX2_CH2_BYT4[7:0] 0xFF Digital mixer 2, ADC channel 2 coefficient byte[7:0]
0x20 ADC_MIX2_CH3_BYT1[7:0] 0x00 Digital mixer 2, ADC channel 3 coefficient byte[31:24]
0x21 ADC_MIX2_CH3_BYT2[7:0] 0x00 Digital mixer 2, ADC channel 3 coefficient byte[23:16]
0x22 ADC_MIX2_CH3_BYT3[7:0] 0x00 Digital mixer 2, ADC channel 3 coefficient byte[15:8]
0x23 ADC_MIX2_CH3_BYT4[7:0] 0x00 Digital mixer 2, ADC channel 3 coefficient byte[7:0]
0x24 ADC_MIX2_CH4_BYT1[7:0] 0x00 Digital mixer 2, ADC channel 4 coefficient byte[31:24]
0x25 ADC_MIX2_CH4_BYT2[7:0] 0x00 Digital mixer 2, ADC channel 4 coefficient byte[23:16]
0x26 ADC_MIX2_CH4_BYT3[7:0] 0x00 Digital mixer 2, ADC channel 4 coefficient byte[15:8]
0x27 ADC_MIX2_CH4_BYT4[7:0] 0x00 Digital mixer 2, ADC channel 4 coefficient byte[7:0]
0x28 ADC_MIX3_CH1_BYT1[7:0] 0x00 Digital mixer 3, ADC channel 1 coefficient byte[31:24]
0x29 ADC_MIX3_CH1_BYT2[7:0] 0x00 Digital mixer 3, ADC channel 1 coefficient byte[23:16]
0x2A ADC_MIX3_CH1_BYT3[7:0] 0x00 Digital mixer 3, ADC channel 1 coefficient byte[15:8]
0x2B ADC_MIX3_CH1_BYT4[7:0] 0x00 Digital mixer 3, ADC channel 1 coefficient byte[7:0]
0x2C ADC_MIX3_CH2_BYT1[7:0] 0x00 Digital mixer 3, ADC channel 2 coefficient byte[31:24]
0x2D ADC_MIX3_CH2_BYT2[7:0] 0x00 Digital mixer 3, ADC channel 2 coefficient byte[23:16]
0x2E ADC_MIX3_CH2_BYT3[7:0] 0x00 Digital mixer 3, ADC channel 2 coefficient byte[15:8]
0x2F ADC_MIX3_CH2_BYT4[7:0] 0x00 Digital mixer 3, ADC channel 2 coefficient byte[7:0]
0x30 ADC_MIX3_CH3_BYT1[7:0] 0x7F Digital mixer 3, ADC channel 3 coefficient byte[31:24]
0x31 ADC_MIX3_CH3_BYT2[7:0] 0xFF Digital mixer 3, ADC channel 3 coefficient byte[23:16]
0x32 ADC_MIX3_CH3_BYT3[7:0] 0xFF Digital mixer 3, ADC channel 3 coefficient byte[15:8]
0x33 ADC_MIX3_CH3_BYT4[7:0] 0xFF Digital mixer 3, ADC channel 3 coefficient byte[7:0]
0x34 ADC_MIX3_CH4_BYT1[7:0] 0x00 Digital mixer 3, ADC channel 4 coefficient byte[31:24]
0x35 ADC_MIX3_CH4_BYT2[7:0] 0x00 Digital mixer 3, ADC channel 4 coefficient byte[23:16]
0x36 ADC_MIX3_CH4_BYT3[7:0] 0x00 Digital mixer 3, ADC channel 4 coefficient byte[15:8]
0x37 ADC_MIX3_CH4_BYT4[7:0] 0x00 Digital mixer 3, ADC channel 4 coefficient byte[7:0]
0x38 ADC_MIX4_CH1_BYT1[7:0] 0x00 Digital mixer 4, ADC channel 1 coefficient byte[31:24]
0x39 ADC_MIX4_CH1_BYT2[7:0] 0x00 Digital mixer 4, ADC channel 1 coefficient byte[23:16]
0x3A ADC_MIX4_CH1_BYT3[7:0] 0x00 Digital mixer 4, ADC channel 1 coefficient byte[15:8]
0x3B ADC_MIX4_CH1_BYT4[7:0] 0x00 Digital mixer 4, ADC channel 1 coefficient byte[7:0]
0x3C ADC_MIX4_CH2_BYT1[7:0] 0x00 Digital mixer 4, ADC channel 2 coefficient byte[31:24]
0x3D ADC_MIX4_CH2_BYT2[7:0] 0x00 Digital mixer 4, ADC channel 2 coefficient byte[23:16]
0x3E ADC_MIX4_CH2_BYT3[7:0] 0x00 Digital mixer 4, ADC channel 2 coefficient byte[15:8]
0x3F ADC_MIX4_CH2_BYT4[7:0] 0x00 Digital mixer 4, ADC channel 2 coefficient byte[7:0]
0x40 ADC_MIX4_CH3_BYT1[7:0] 0x00 Digital mixer 4, ADC channel 3 coefficient byte[31:24]
0x41 ADC_MIX4_CH3_BYT2[7:0] 0x00 Digital mixer 4, ADC channel 3 coefficient byte[23:16]
0x42 ADC_MIX4_CH3_BYT3[7:0] 0x00 Digital mixer 4, ADC channel 3 coefficient byte[15:8]
0x43 ADC_MIX4_CH3_BYT4[7:0] 0x00 Digital mixer 4, ADC channel 3 coefficient byte[7:0]
0x44 ADC_MIX4_CH4_BYT1[7:0] 0x7F Digital mixer 4, ADC channel 4 coefficient byte[31:24]
0x45 ADC_MIX4_CH4_BYT2[7:0] 0xFF Digital mixer 4, ADC channel 4 coefficient byte[23:16]
0x46 ADC_MIX4_CH4_BYT3[7:0] 0xFF Digital mixer 4, ADC channel 4 coefficient byte[15:8]
0x47 ADC_MIX4_CH4_BYT4[7:0] 0xFF Digital mixer 4, ADC channel 4 coefficient byte[7:0]
0x78 ADC_IIR_N0_BYT1[7:0] 0x7F Programmable ADC first-order IIR, N0 coefficient byte[31:24]
0x79 ADC_IIR_N0_BYT2[7:0] 0xFF Programmable ADC first-order IIR, N0 coefficient byte[23:16]
0x7A ADC_IIR_N0_BYT3[7:0] 0xFF Programmable ADC first-order IIR, N0 coefficient byte[15:8]
0x7B ADC_IIR_N0_BYT4[7:0] 0xFF Programmable ADC first-order IIR, N0 coefficient byte[7:0]
0x7C ADC_IIR_N1_BYT1[7:0] 0x00 Programmable ADC first-order IIR, N1 coefficient byte[31:24]
0x7D ADC_IIR_N1_BYT2[7:0] 0x00 Programmable ADC first-order IIR, N1 coefficient byte[23:16]
0x7E ADC_IIR_N1_BYT3[7:0] 0x00 Programmable ADC first-order IIR, N1 coefficient byte[15:8]
0x7F ADC_IIR_N1_BYT4[7:0] 0x00 Programmable ADC first-order IIR, N1 coefficient byte[7:0]