The TAC5111-Q1 consists of two pairs of analog input pins (INxP and INxM) that can be configured as differential inputs or single-ended inputs for the recording channel. The device supports recording of up to one analog channel and integrates an input swap feature (ADC_CH_SWAP (P0_R119_D[1])) to select the input pins for recording between the IN1x and IN2x using the high-performance single-channel ADC. The input source for the analog pins can be from electret condenser analog microphones, microelectrical-mechanical system (MEMS) analog microphones, or line-in (auxiliary) inputs from the system board. Analog inputs support differential input, single-ended inputs (two pin and one-pin) with AC and DC coupling options. Table 6-13 shows the input source selection for the record channel 1.

Typically, voice or audio signal inputs are capacitively coupled (AC-coupled) to the device and the common-mode variation at the device input is limited to less than 100mVpp for differential inputs for best performance. However, for applications that cannot avoid large common-mode fluctuations or when needed to save board space, the device also supports options for increasing the common mode tolerance and for DC-coupled inputs. This configuration can be done by setting the input common mode tolerance in ADC_CH1_CM_TOL (P0_R80_D[3:2]) register bits. Table 6-10 shows these options for Channel 1. Setting higher common mode tolerance offers improved CMRR performance at the expense of noise performance by a few decibels.

See Figure 6-15 to Figure 6-20 for the various typical input configuration diagrams. For single-ended inputs, the INxM pin can be directly grounded in DC-coupled configuration, but the INxM pin must be grounded after the AC-coupling capacitor in the AC-coupled configuration. For the best dynamic range performance, the differential AC-coupled input setting should be used and the common-mode variation at the device input should be limited to less than 100mVpp. For more details, refer Analog Input Configurations, Mixing and Muxing of TAx5x1x Devices application report.

The device also allows for flexibility in choosing the typical input impedance on INxP or INxM from 5kΩ (default), 10kΩ, and 40kΩ based on the input source impedance selection. There can be a ±20% variation on the selected input impedance value. The higher input impedance results in slightly higher noise or lower dynamic range. Table 6-12 lists the configuration register settings for the input impedance for the record channel.

Input impedance setting of 5 kΩ is not supported when the ADC inputs are configured for single ended mux (ADC_CHx_INSRC = 2'b10 or 2'b11) and also not supported in the high swing mode (Section 6.3.5).

The value of the coupling capacitor in AC-coupled mode must be chosen so that the high-pass filter formed by the coupling capacitor and the input impedance do not affect the signal content. Before proper recording can begin, this coupling capacitor must be charged up to the common-mode voltage at power-up. To enable quick charging, the device has modes to speed up the charging of the coupling capacitor. The default value of the quick-charge timing is set for a coupling capacitor up to 1 µF. However, if a higher-value capacitor is used in the system, then the quick-charging timing can be increased by using the INCAP_QCHG (P0_R5_D[7:6]) register bits. For low distortion performance, use the low-voltage coefficient capacitors for AC coupling.

Additionally, if the application uses digital PDM microphones for the recording, GPIOx, GPI1 and GPO1 pins can be reconfigured in the device to support up to four channels for the digital microphone recording (when the analog channels are not used). The device can also support simultaneous recording on one analog channel and three digital microphone channels. These combinations can be enabled using the INTF4_CFG (B0_P0_R19) register. More details on enabling the PDM channels are present Section 6.3.7.

The TAC5111-Q1 also supports an incremental mode of ADC where analog input channels can be used for DC measurements. This can be configured by setting IADC_EN (P0_R81_D[7]). For more details on the incremental mode of ADC, refer Section 6.3.8.