SLASF23A December   2023  – January 2025 TAC5212

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Table
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: I2C Interface
    7. 6.7  Switching Characteristics: I2C Interface
    8. 6.8  Timing Requirements: SPI Interface
    9. 6.9  Switching Characteristics: SPI Interface
    10. 6.10 Timing Requirements: TDM, I2S or LJ Interface
    11. 6.11 Switching Characteristics: TDM, I2S or LJ Interface
    12. 6.12 Timing Requirements: PDM Digital Microphone Interface
    13. 6.13 Switching Characteristics: PDM Digital Microphone Interface
    14. 6.14 Timing Diagrams
    15. 6.15 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Serial Interfaces
        1. 7.3.1.1 Control Serial Interfaces
        2. 7.3.1.2 Audio Serial Interfaces
          1. 7.3.1.2.1 Time Division Multiplexed Audio (TDM) Interface
          2. 7.3.1.2.2 Inter IC Sound (I2S) Interface
          3. 7.3.1.2.3 Left-Justified (LJ) Interface
        3. 7.3.1.3 Using Multiple Devices With Shared Buses
      2. 7.3.2  Phase-Locked Loop (PLL) and Clock Generation
      3. 7.3.3  Input Channel Configurations
      4. 7.3.4  Output Channel Configurations
      5. 7.3.5  Reference Voltage
      6. 7.3.6  Programmable Microphone Bias
      7. 7.3.7  Digital PDM Microphone Record Channel
      8. 7.3.8  Incremental ADC (IADC) Mode
      9. 7.3.9  Signal-Chain Processing
        1. 7.3.9.1 ADC Signal-Chain
          1. 7.3.9.1.1  6 to 4 Input Select Multiplexer (6:4 MUX)
          2. 7.3.9.1.2  Programmable Channel Gain and Digital Volume Control
          3. 7.3.9.1.3  Programmable Channel Gain Calibration
          4. 7.3.9.1.4  Programmable Channel Phase Calibration
          5. 7.3.9.1.5  Programmable Digital High-Pass Filter
          6. 7.3.9.1.6  Programmable Digital Biquad Filters
          7. 7.3.9.1.7  Programmable Channel Summer and Digital Mixer
          8. 7.3.9.1.8  Configurable Digital Decimation Filters
            1. 7.3.9.1.8.1 Linear-phase filters
              1. 7.3.9.1.8.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 7.3.9.1.8.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 7.3.9.1.8.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 7.3.9.1.8.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 7.3.9.1.8.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 7.3.9.1.8.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 7.3.9.1.8.1.7 Sampling Rate: 192kHz or 176.4kHz
            2. 7.3.9.1.8.2 Low-latency Filters
              1. 7.3.9.1.8.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.1.8.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.1.8.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.1.8.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.1.8.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 7.3.9.1.8.3 Ultra Low-latency Filters
              1. 7.3.9.1.8.3.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.1.8.3.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.1.8.3.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.1.8.3.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.1.8.3.5 Sampling Rate: 192kHz or 176.4kHz
          9. 7.3.9.1.9  Automatic Gain Controller (AGC)
          10. 7.3.9.1.10 Voice Activity Detection (VAD)
          11. 7.3.9.1.11 Ultrasonic Activity Detection (UAD)
        2. 7.3.9.2 DAC Signal-Chain
          1. 7.3.9.2.1 Programmable Channel Gain and Digital Volume Control
          2. 7.3.9.2.2 Programmable Channel Gain Calibration
          3. 7.3.9.2.3 Programmable Digital High-Pass Filter
          4. 7.3.9.2.4 Programmable Digital Biquad Filters
          5. 7.3.9.2.5 Programmable Digital Mixer
          6. 7.3.9.2.6 Configurable Digital Interpolation Filters
            1. 7.3.9.2.6.1 Linear-phase filters
              1. 7.3.9.2.6.1.1 Sampling Rate: 8kHz or 7.35kHz
              2. 7.3.9.2.6.1.2 Sampling Rate: 16kHz or 14.7kHz
              3. 7.3.9.2.6.1.3 Sampling Rate: 24kHz or 22.05kHz
              4. 7.3.9.2.6.1.4 Sampling Rate: 32kHz or 29.4kHz
              5. 7.3.9.2.6.1.5 Sampling Rate: 48kHz or 44.1kHz
              6. 7.3.9.2.6.1.6 Sampling Rate: 96kHz or 88.2kHz
              7. 7.3.9.2.6.1.7 Sampling Rate: 192kHz or 176.4kHz
              8. 7.3.9.2.6.1.8 Sampling Rate: 384kHz or 352.8kHz
              9. 7.3.9.2.6.1.9 Sampling Rate 768kHz or 705.6kHz
            2. 7.3.9.2.6.2 Low-latency Filters
              1. 7.3.9.2.6.2.1 Sampling Rate: 24kHz or 22.05kHz
              2. 7.3.9.2.6.2.2 Sampling Rate: 32kHz or 29.4kHz
              3. 7.3.9.2.6.2.3 Sampling Rate: 48kHz or 44.1kHz
              4. 7.3.9.2.6.2.4 Sampling Rate: 96kHz or 88.2kHz
              5. 7.3.9.2.6.2.5 Sampling Rate: 192kHz or 176.4kHz
            3. 7.3.9.2.6.3 Ultra-Low-Latency Filters
              1. 7.3.9.2.6.3.1 Sampling Rate: 24 kHz or 22.05 kHz
              2. 7.3.9.2.6.3.2 Sampling Rate: 32 kHz or 29.4 kHz
              3. 7.3.9.2.6.3.3 Sampling Rate: 48 kHz or 44.1 kHz
              4. 7.3.9.2.6.3.4 Sampling Rate: 96 kHz or 88.2 kHz
              5. 7.3.9.2.6.3.5 Sampling Rate 192 kHz or 176.4 kHz
      10. 7.3.10 Interrupts, Status, and Digital I/O Pin Multiplexing
      11. 7.3.11 Power Tune Mode
    4. 7.4 Device Functional Modes
      1. 7.4.1 Sleep Mode or Software Shutdown
      2. 7.4.2 Active Mode
      3. 7.4.3 Software Reset
    5. 7.5 Programming
      1. 7.5.1 Control Serial Interfaces
        1. 7.5.1.1 I2C Control Interface
          1. 7.5.1.1.1 General I2C Operation
          2. 7.5.1.1.2 I2C Single-Byte and Multiple-Byte Transfers
            1. 7.5.1.1.2.1 I2C Single-Byte Write
            2. 7.5.1.1.2.2 I2C Multiple-Byte Write
            3. 7.5.1.1.2.3 I2C Single-Byte Read
            4. 7.5.1.1.2.4 I2C Multiple-Byte Read
        2. 7.5.1.2 SPI Control Interface
  9. 8 Register Maps
    1. 8.1 Device Configuration Registers
      1. 8.1.1 Book0_P0 Registers
      2. 8.1.2 B0_P1 Registers
      3. 8.1.3 Book0_Page3 Registers
    2. 8.2 Programmable Coefficient Registers
      1. 8.2.1  Programmable Coefficient Registers: Page 8
      2. 8.2.2  Programmable Coefficient Registers: Page 9
      3. 8.2.3  Programmable Coefficient Registers: Page 10
      4. 8.2.4  Programmable Coefficient Registers: Page 11
      5. 8.2.5  Programmable Coefficient Registers: Page 15
      6. 8.2.6  Programmable Coefficient Registers: Page 16
      7. 8.2.7  Programmable Coefficient Registers: Page 17
      8. 8.2.8  Programmable Coefficient Registers: Page 18
      9. 8.2.9  Programmable Coefficient Registers: Page 19
      10. 8.2.10 Programmable Coefficient Registers: Page 25
      11. 8.2.11 Programmable Coefficient Registers: Page 26
      12. 8.2.12 Programmable Coefficient Registers: Page 27
      13. 8.2.13 Programmable Coefficient Registers: Page 28
  10. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Application
      2. 9.2.2 Design Requirements
      3. 9.2.3 Detailed Design Procedure
      4. 9.2.4 Application Performance Plots
      5. 9.2.5 Example Device Register Configuration Script for EVM Setup
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 AVDD_MODE for 1.8V Operation
      2. 9.3.2 IOVDD_IO_MODE for 1.8V and 1.2V Operation
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Support Resources
    4. 10.4 Trademarks
    5. 10.5 Electrostatic Discharge Caution
    6. 10.6 Glossary
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
7.3.9.1.9 Automatic Gain Controller (AGC)

The device includes an automatic gain controller (AGC) for ADC recording. As shown in Figure 7-68, the AGC can be used to maintain a nominally constant output level when recording speech. Instead of manually setting the channel gain in AGC mode, the circuitry automatically adjusts the channel gain when the input signal becomes overly loud or very weak, such as when a person speaking into a microphone moves closer to or farther from the microphone. The AGC algorithm has several programmable parameters, including target level, maximum gain allowed, attack and release (or decay) time constants, and noise thresholds that allow the algorithm to be fine-tuned for any particular application. These are part of the programmable coefficients of the device for flexibility and can be configured using the registers in Section 8.2.12 and Section 8.2.13.

TAC5212 AGC Characteristics Figure 7-68 AGC Characteristics

The target level (AGC_LVL) represents the nominal approximate output level at which the AGC attempts to hold the ADC output signal level. The TAC5212 allows programming of different target levels. The target level is recommended to be set with enough margin to prevent clipping when loud sounds occur. For further details on the AGC various configurable parameter and application use, see Using the Automatic Gain Controller (AGC) in TAx5x1x Family application report. TI recommends using the PPC3 GUI for configuring the programmable coefficients settings; for more details see the TAC5212EVM-PDK Evaluation module user's guide and the PurePath™ console graphical development suite.