SLOS998A Data sheet

SLOS998A December 2020 – September 2021 TAS2764

PRODUCTION DATA

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Mechanical Data (Package|Pins)

YBH|30
- MXBG430

Thermal pad, mechanical data (Package|Pins)

Orderable Information

6.5 Electrical Characteristics

T_A = 25 °C, PVDD = 12 V, VBAT1S = 3.8 V, AVDD = 1.8V IOVDD =1.2 V, R_L = 4Ω + 16µH, f_in = 1 kHz, f_s = 48 kHz, Gain = 21 dBV, SDZ = 1, EDGE_RATE[1:0]=00, NG_EN=0, EN_LLSR=1, PWR_MODE1, Measured filter free as in Section 7 (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DIGITAL INPUT and OUTPUT
V_IH	High-level digital input logic voltage threshold	All digital pins except SDA and SCL	0.7×IOVDD			V
V_IL	Low-level digital input logic voltage threshold	All digital pins except SDA and SCL			0.3 × IOVDD	V
V_IH(I2C)	High-level digital input logic voltage threshold	SDA and SCL	0.7xIOVDD			V
V_IL(I2C)	Low-level digital input logic voltage threshold	SDA and SCL			0.3 x IOVDD	V
V_OH	High-level digital output voltage	All digital pins except SDA, SCL and IRQZ; I_OH = 100 µA.	IOVDD–0.2V			V
V_OL	Low-level digital output voltage	All digital pins except SDA, SCL and IRQZ; I_OL = –100 µA.			0.2	V
V_OL(I2C)	Low-level digital output voltage	SDA and SCL; I_OL(I2C) = -1 mA.	-		0.2 x IOVDD	V
V_OL(IRQZ)	Low-level digital output voltage for IRQZ open drain Output	IRQZ; I_OL(IRQZ) = -1 mA.			0.2	V
I_IH	Input logic-high leakage for digital inputs	All digital pins; Input = IOVDD.	–1		1	µA
I_IL	Input logic-low leakage for digital inputs	All digital pins; Input = GND.	–1		1	µA
R_OS	OUT to VSNS Resistors	Load disconnected		10		kΩ
C_IN	Input capacitance for digital inputs	All digital pins		5		pF
R_PD	Pull down resistance for IO pins when asserted on	SDOUT, SDIN, FSYNC, SBCLK		18		kΩ
IO	Output Current Strength	Drive Mode 0 - Measured at (IOVDD-0.4V) and 0.4V		8		mA
		Drive Mode 1 - Measured at (IOVDD-0.4V) and 0.4V		6
		Drive Mode 2 - Measured at (IOVDD-0.4V) and 0.4V		4
		Drive Mode 3 - Measured at (IOVDD-0.4V) and 0.4V		2
AMPLIFIER PERFORMANCE
P_OUT	Maximum Output Power	R_L = 4Ω + 16µH, THD+N = 1 %		13		W
		R_L = 8 Ω + 16 µH, THD+N = 1 %		8
		R_L = 4Ω + 16µH, THD+N = 10 %		15.8
		R_L = 8 Ω + 16 µH, THD+N = 10 %		9.7
	System Efficiency	R_L = 4Ω + 16µH, P_OUT = 1 W		80.5		%
		R_L = 8 Ω + 16 µH, P_OUT = 1 W		84
		R_L = 8 Ω + 5µH, P_OUT = 1 W PWR_MODE2		76.5
		R_L = 8 Ω + 16µH, P_OUT = 1 W PWR_MODE2		82.5
		R_L = 4Ω + 16µH, P_OUT = 10 W		85
		R_L = 8 Ω + 16 µH, P_OUT = 5 W		90
		R_L = 8 Ω + 5 µH, P_OUT = 8 W, PWR_MODE2		90
THD+N	Total Harmonic Distortion and Noise	P_OUT = 1 W, R_L = 4Ω + 16µH, f_in = 1 kHz		-83		dB
		P_OUT = 1 W, R_L = 4Ω + 16µH, f_in = 6.67 kHz		-83
		POUT = 1 W, RL = 8 Ω + 5µH, fin = 20 Hz - 20 kHz, PWR_MODE2		-83
IMD	Intermodulation Distortion	ITU-R, 19kHz/20kHz, 1:1:6.5W		-80		dB
V_N	Idle Channel Noise	A-Weighted, 20 Hz - 20 kHz, DAC in Mute, PWR_MODE1		27		µV
		A-Weghted, 20 Hz - 20k Hz, DAC in Mute, PWR_MODE2		27
		A-Weighted, 20 Hz - 20 kHz, DAC in Mute, PWR_MODE4		32.7
F_PWM	Class-D PWM Switching Frequency	Average frequency in Spread Spectrum Mode, CLASSD_SYNC=0		384		kHz
		Fixed Frequency Mode, CLASSD_SYNC=0	365	384	404
		Fixed Frequency Mode, CLASSD_SYNC=1, f_s = 44.1, 88.2 kHz		352.8
		Fixed Frequency Mode, CLASSD_SYNC=1, f_s = 48, 96 kHz		384
V_OS	Output Offset Voltage	Idle Mode	-1		1	mV
DNR	Dynamic Range	A-Weighted, -60 dBFS		109		dB
DNR	Dynamic Range	A-Weighted, -60 dBFS, PWR_MODE2		109		dB
SNR	Signal to Noise Ratio	A-Weighted, Referenced to 1 % THD+N Output Level		109		dB
SNR	Signal to Noise Ratio	A-Weighted, Referenced to 1 % THD+N Output Level PWR_MODE2		109		dB
K_CP	Click and Pop Performance	Into and out of Shutdown, A-weighted		1	2.7	mV
	Full Scale Output Voltage	f_s <= 48kHz		21		dBV
	Minimum Programmable Gain	f_s <= 48kHz		11		dBV
	Maximum Programmable Gain	f_s <= 48kHz		21		dBV
	Programmable Output Level Step Size			0.5		dB
	Mute attenuation	Device in Software Shutdown or Muted in Normal Operation		110		dB
	Chip to Chip Group Delay		-1		1	µs
	EMI Margin to EN55022B	6" cable, Pout = 1W		-6		dB
	PVDD Power Supply Rejection Ratio	PVDD = 12 V + 200 mV_pp, f_ripple = 217 Hz		100		dB
		PVDD = 12 V + 200 mV_pp, f_ripple = 1 kHz		112
		PVDD = 12 V + 200 mV_pp, f_ripple = 20 kHz		96
	VBAT1S Power Supply Rejection Ratio	VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 217 Hz		100		dB
		VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 1 kHz		112
		VBAT1S = 3.8 V + 200 mV_pp, f_ripple = 20 kHz		88
	AVDD Power Supply Rejection Ratio	AVDD = 1.8 V + 200 mV_pp, f_ripple = 217 Hz		96		dB
		AVDD = 1.8 V + 200 mV_pp, f_ripple = 1 kHz		90
		AVDD = 1.8 V + 200 mV_pp, f_ripple = 20 kHz		96
	Power Supply Intermodulation	PVDD 217 Hz, 100-mVpp, Input f=1kHz @ 400mW		-70		dB
		VBAT1S 217 Hz, 100-mVpp, Input f=1kHz @ 400mW		-118
		AVDD, 217 Hz, 100-mVpp, Input f=1kHz @ 400mW		-82
		IOVDD 217 Hz, 100-mVpp, Input f=1kHz @ 400mW		-70
	Turn ON Time from Release of SW Shutdown	No Volume Ramping		1.2		ms
	Turn ON Time from Release of SW Shutdown	Volume Ramping		5.3		ms
	Turn OFF Time From Assertion of SW Shutdown to Amp Hi-Z	No Volume Ramping		0.5		ms
	Turn OFF Time From Assertion of SW Shutdown to Amp Hi-Z	Volume Ramping		5.9		ms
	Release of SW Shutdown to new assertion of SW Shutdown		1.5			ms
	Out of HW Shutdown to first I²C command		1			ms
	Noise Gate recovery to Shutdown latency		100			μs
	Power up to BOP_SHDN latency		1.5			ms
DIAGNOSTIC GENERATOR
THD+N	Total Harmonic Distortion and Noise	Pout=1W, DVC_LVL[7:0]=17h		-80		dB
f_err	Frequency Error	Using internal oscillator			5	%
DIE TEMPERATURE SENSOR
	Resolution			8		bits
	Minimum Die Temperature Measurement			-40		°C
	Maximum Die Temperature Measurement			150		°C
	Die Temperature Resolution			1		°C
	Die Temperature Accuracy		-5		5	°C
VOLTAGE MONITOR
	Resolution			12		bits
	Minimum PVDD Measurement			2		V
	Maximum PVDD Measurements			16		V
	PVDD Resolution			20		mV
	PVDD Accuracy		-100		100	mV
	Minimum VBAT1S Measurement			2		V
	Maximum VBAT1S Measurement			6		V
	VBAT1S Resolution			20		mV
	VBAT1S Accuracy		-45		45	mV
TDM SERIAL AUDIO PORT
	PCM Sample Rates and FSYNC Input Frequency	Typical values	44.1		96	kHz
	SBCLK Input Frequency	I²S/TDM Operation	0.7056		24.576	MHz
	SBCLK Maximum Input Jitter	RMS Jitter below 40 kHz that can be tolerated without performance degradation			0.5	ns
	SBCLK Maximum Input Jitter	RMS Jitter above 40 kHz that can be tolerated without performance degradation			1	ns
	SBCLK Cycles per FSYNC in I²S and TDM Modes	Other values: 24, 32, 48, 64, 96, 125, 128, 192, 250, 256, 384, 500	16		512	Cycles
PCM PLAYBACK CHARACTERISTICS f_s ≤ 48 kHz
f_s	Sample Rates		44.1		48	kHz
	Passband Frequency Meeting Ripple			0.454		f_s
	Passband Ripple	20Hz to LPF cutoff frequency	-0.3		+0.3	dB
	Stop Band Attenuation	≥ 0.55 f_s		60		dB
	Stop Band Attenuation	≥ 1 f_s		65		dB
	Group Delay @ 1kHz	Noise Gate Enabled		17.7		1/f_s
	Group Delay @ 1kHz	Noise Gate Disabled		9		1/f_s
	Group Delay	DC to 0.454 f_s , Noise Gate enabled, DC blocker disabled	16		19	1/f_s
	Group Delay	DC to 0.454 f_s , Noise Gate disabled, DC blocker disabled	7		10	1/f_s
f_s > 48 kHz
fs	Sample Rates		88.2		96	kHz
	Passband Frequency Meeting Ripple	f_s = 96 kHz		0.375		f_s
	Passband 3db Frequency	f_s = 96 kHz		0.409		f_s
	Passband Ripple	DC to LPF cutoff frequency	-0.5		0.5	dB
	Stop Band Attenuation	≥ 0.55 f_s		60		dB
	Stop Band Attenuation	≥ 1 f_s		65		dB
	Group Delay @ 1kHz	Noise Gate Enabled		33.2		1/f_s
	Group Delay @ 1kHz	Noise Gate Disabled		17.4		1/f_s
	Group Delay	DC to 0.375 f_s for 96 kHz, Noise Gate Enabled, DC blocker disabled	33		39	1/f_s
	Group Delay	DC to 0.375 f_s for 96 kHz, Noise Gate Disabled, DC blocker disabled	17		23	1/f_s
SPEAKER CURRENT SENSE
	Resolution			16		bits
DNR	Dynamic Range	Un-Weighted, Relative to 0 dBFS		66		dB
THD+N	Total Harmonic Distortion and Noise	f_in = 1 kHz, Pout = 7. 5W		-58		dB
	Full Scale Input Current	-6dBFS Input Signal Level		3.75		A
	Differential Mode Gain	Pout = 1W, using a 40Hz, -40dBFS pilot tone	0.98		1.02
	Differential Mode Gain Variability	Pout = 100mW to 0.1% THD+N, using a 40Hz, -40dBFS pilot tone, Calibrated at 100 mW	-1.4		1.4	%
	Gain Error Over Temperature	-20⁰C to 70⁰C, Pout=1W, Calibrated at 25⁰C	-1.35		1.35	%
	Offset	HPF_FREQ_REC[2:0]=0h	-2		2	mA
	Frequency Response	20Hz-20kHz	-0.1		0.1	dB
	Group Delay			8		1/f_s
SPEAKER VOLTAGE SENSE
	Resolution			16		bits
DNR	Dynamic Range	Un-Weighted, Relative 0 dBFS		69		dB
THD+N	Total Harmonic Distortion and Noise	f_in = 1 kHz, Pout = 7.5W		-60		dB
	Full Scale Input Voltage			14		V_PK
	Differential Mode Gain	Pout = 1W, using a 40Hz - 40dBFS pilot tone	0.99		1.01
	Differential Mode Gain Variability	Pout = 100mW to 0.1% THD+N, using a 40Hz, -40dBFS pilot tone	-0.45		+0.45	%
	Gain error over temperature	-20C to 70C, Pout=1W	-0.75		+0.75	%
	Offset	HPF_FREQ_REC[2:0]=0h	-10		+10	mV
	Frequency Response	20Hz - 20kHz	-0.1		0.1	dB
	Group Delay			8		1/f_s
SPEAKER VOLTAGE to CURRENT SENSE PHASE
	Phase Error between V and I			300		ns
PROTECTION CIRCUITRY
	Brownout Prevention Latency to First Attack	PWR_MODE2, Measured at BOP_TH0 of 8.25V		15		µs
	Thermal Shutdown Temperature -Typical values		135	145	155	°C
	Output Over Current Limit on PVDD	Output to Output, Output to GND, Output to PVDD		5.9		A
	Output Overt Current Limit on VBAT1S	Output to Output, Output to GND		2.5		A
	VBAT1S Undervoltage Lockout Threshold	UVLO is asserted	2			V
	VBAT1S Undervoltage Lockout Threshold	UVLO is de-asserted			2.3	V
	AVDD Undervoltage Lockout Threshold	UVLO is asserted	1.4			V
	AVDD Undervoltage Lockout Threshold	UVLO is de-asserted			1.6	V
	IOVDD Undervoltage Lockout Threshold	UVLO is asserted	0.7			V
	IOVDD Undervoltage Lockout Threshold	UVLO is de-asserted			1.1	V
	VBAT1S Internal LDO Undervoltage Lockout Threshold	UVLO is asserted	4			V
	VBAT1S Internal LDO Overvoltage Lockout Threshold	OVLO is asserted			5.5	V

TYPICAL CURRENT CONSUMPTION
	Hardware Shutdown	SDZ = 0, PVDD		0.1		µA
		SDZ = 0, VBAT1S		0.1
		SDZ = 0, AVDD		1
		SDZ = 0, IOVDD		0.1
	Software Shutdown	All Clocks Stopped, PVDD		0.1		µA
		All Clocks Stopped, VBAT1S		1
		All Clocks Stopped, AVDD		10
		All Clocks Stopped, IOVDD		1
	Noise Gate Mode	f_s = 48 kHz, PVDD		0.05		mA
		f_s = 48 kHz, VBAT1S		0.14
		f_s = 48 kHz, AVDD		3.2
		f_s = 48 kHz, IOVDD		0.1
	Idle Mode - PWR_MODE1, PWR_MODE3	f_s = 48 kHz, PVDD		0.02		mA
		f_s = 48 kHz, VBAT1S		3
		f_s = 48 kHz, AVDD		8.9
		f_s = 48 kHz, IOVDD		0.1
	Idle Mode - PWR_MODE2	f_s = 48 kHz, PVDD		3.2		mA
		f_s = 48 kHz, AVDD		9.3
		f_s = 48 kHz, IOVDD		0.1
	Idle Mode - PWR_MODE4	f_s = 48 kHz, PVDD		4.1		mA
		f_s = 48 kHz, AVDD		9.3
		f_s = 48 kHz, IOVDD		0.1
	Idle Mode - PWR_MODE1, PWR_MODE3	f_s = 48 kHz, AVDD, IV Sense Disabled		6.3

* For definition of power modes see Section 11.1.