SLOS814D March   2014  – September 2016 TAS5421-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. I2C Bus Protocol
        2. Random Write
        3. Random Read
        4. Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Amplifier Output Filtering
        2. Amplifier Output Snubbers
        3. Bootstrap Capacitors
        4. Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. Unused Pin Connections
          1. MUTE Pin
          2. STANDBY Pin
          3. I2C Pins (SDA and SCL)
          4. Terminating Unused Outputs
          5. Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Top Layer
      2. 10.2.2 Second Layer - Signal Layer
      3. 10.2.3 Third Layer - Power Layer
      4. 10.2.4 Bottom Layer - Ground Layer
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7 Detailed Description

7.1 Overview

The TAS5421-Q1 is a mono analog-input audio amplifier for use in the automotive environment. The design uses an ultra-efficient class-D technology developed by Texas Instruments, but with features added for the automotive industry. The class-D technology allows for reduced power consumption, reduced heat, and reduced peak currents in the electrical system. The device realizes an audio sound system design with smaller size and lower weight than traditional class-AB solutions.

The TAS5421-Q1 device has seven core design blocks:

  • PWM
  • Gate drive
  • Power FETs
  • Diagnostics
  • Protection
  • Power supply
  • I2C serial communication bus

7.2 Functional Block Diagram

TAS5421-Q1 fbd_SLOS814.gif

7.3 Feature Description

7.3.1 Analog Audio Input and Preamplifier

The differential input stage of the amplifier cancels common-mode noise that appears on the inputs. For a differential audio source, connect the positive lead to IN_P and the negative lead to IN_N. The inputs must be ac-coupled to minimize the output dc-offset and ensure correct ramping of the output voltages. For good transient performance, the impedance seen at each of the two differential inputs should be the same.

The gain setting impacts the analog input impedance of the amplifier. See Table 1 for typical values.

Table 1. Input Impedance and Gain

Gain Input Impedance
20 dB 60 kΩ ± 20%
26 dB 30 kΩ ± 20%
32 dB 15 kΩ ± 20%
36 dB 9 kΩ ± 20%

7.3.2 Pulse-Width Modulator (PWM)

The PWM converts the analog signal from the preamplifier into a switched signal of varying duty cycle. This is the critical stage that defines the class-D architecture. In the TAS5421-Q1, the modulator is an advanced design with high bandwidth, low noise, low distortion, and excellent stability.

The pulse-width modulation scheme allows increased efficiency at low power. Each output is switching from 0 V to PVDD. The OUTP and OUTN pins are in phase with each other with no input so that there is little or no current in the speaker. The duty cycle of OUTP is greater than 50% and the duty cycle OUTN is less than 50% for positive output voltages. The duty cycle of OUTN is greater than 50% and the duty cycle of OUTP is less than 50% for negative output voltages. The voltage across the load is at 0 V through most of the switching period, reducing power loss.

TAS5421-Q1 BD_Modulation_SLOS814.gif Figure 10. BD Mode Modulation

7.3.3 Gate Drive

The gate driver accepts the low-voltage PWM signal and level-shifts the signal to drive a high-current, full-bridge, power FET stage. The device uses proprietary techniques to optimize EMI and audio performance.

7.3.4 Power FETs

The BTL output comprises four matched N-channel FETs for high efficiency and maximum power transfer to the load. By design, the FETs withstand large voltage transients during a load-dump event.

7.3.5 Load Diagnostics

The device incorporates load diagnostic circuitry designed for detecting and determining the status of output connections. The device supports the following diagnostics:

  • Short to GND
  • Short to PVDD
  • Short across load
  • Open load

The device reports the presence of any of the short or open conditions to the system via I2C register read.

  1. Load Diagnostics—The load diagnostic function runs on de-assertion of STANDBY or when the device is in a fault state (dc detect, overcurrent, overvoltage, undervoltage, and overtemperature). During this test, the outputs are in a Hi-Z state. The device determines whether the output is a short to GND, short to PVDD, open load, or shorted load. The load diagnostic biases the output, which therefore requires limiting the capacitance value for proper functioning; see the Recommended Operating Conditions. The load diagnostic test takes approximately 229 ms to run. Note that the check phase repeats up to five times if a fault is present or a large capacitor to GND is present on the output. On detection of an open load, the output still operates. On detection of any other fault condition, the output goes into a Hi-Z state, and the device checks the load continuously until removal of the fault condition. After detection of a normal output condition, the audio output starts. The load diagnostics run after every other overvoltage (OV) event. The load diagnostic for open load only has I2C reporting. All other faults have I2C and FAULT pin assertion.
    The device performs load diagnostic tests as shown in Figure 11.
    Figure 12 illustrates how the diagnostics determine the load based on output conditions.
  2. TAS5421-Q1 ld-diag-tim_SLOS814.gif Figure 11. Load Diagnostics Sequence of Events
    TAS5421-Q1 ld-dia-thr_SLOS814.gif Figure 12. Load Diagnostic Reporting Thresholds
  3. Faults During Load Diagnostics—If the device detects a fault (such as overtemperature, overvoltage, or undervoltage) during the load diagnostics test, the device exits the load diagnostics, which can result in a pop or click on the output.

7.3.6 Protection and Monitoring

  • Overcurrent Shutdown (OCSD)—The overcurrent shutdown forces the output into Hi-Z. The device asserts the FAULT pin and updates the I2C register.
  • DC Detect—This circuit checks for a dc offset continuously during normal operation at the output of the amplifier. If a dc offset occurs, the device asserts the FAULT pin and updates the I2C register. Note that the dc detection threshold follows PVDD changes.
  • Overtemperature Shutdown (OTSD)—The device shuts down when the die junction temperature reaches the overtemperature threshold. The device asserts the FAULT pin asserts and updates I2C register. Recovery is automatic when the temperature returns to a safe level.
  • Undervoltage (UV)—The undervoltage (UV) protection detects low voltages on PVDD. In the event of an undervoltage condition, the device asserts the FAULT pin and resets the I2C register.
  • Power-On Reset (POR)—Power-on reset (POR) occurs when PVDD drops below the POR threshold. A POR event causes the I2C bus to go into a high-impedance state. After recovery from the POR event, the device restarts automatically with default I2C register settings. The I2C is active as long as the device is not in POR.
  • Overvoltage (OV) and Load Dump—OV protection detects high voltages on PVDD. If PVDD reaches the overvoltage threshold, the device asserts the FAULT pin and updates the I2C register. The device can withstand 40-V load-dump voltage spikes.
  • SpeakerGuard—This protection circuitry limits the output voltage to the value selected in I2C register 0x03. This value determines both the positive and negative limits. The user can use the SpeakerGuard feature to improve battery life or protect the speaker from exceeding its excursion limits.
  • Adjacent-Pin Shorts—The device design is such that shorts between adjacent pins do not cause damage.

7.3.7 I2C Serial Communication Bus

The device communicates with the system processor via the I2C serial communication bus as an I2C slave-only device. The processor can poll the device via I2C to determine the operating status. All reports of fault conditions and detections are via I2C. The system can also set numerous features and operating conditions via I2C. The I2C interface is active approximately 1 ms after the STANDBY pin is high.

The I2C interface controls the following device features:

  • Changing gain setting to 20 dB, 26 dB, 32 dB, or 36 dB.
  • Controlling peak voltage value of SpeakerGuard protection circuitry
  • Reporting load diagnostic results
  • Changing of switching frequency for AM radio avoidance I2C Bus Protocol

The device has a bidirectional serial control interface that is compatible with the Inter IC (I2C) bus protocol and supports 400-kbps data transfer rates for random and sequential write and read operations. This is a slave-only device that does not support a multimaster bus environment or wait-state insertion. The master device uses the I2C control interface to program the registers of the device and to read device status.

The I2C bus employs two signals, SDA (data) and SCL (clock), to communicate between integrated circuits in a system. Data transfer on the bus is serial, one bit at a time. The transfer of address and data is in byte (8-bit) format with the most-significant bit (MSB) transferred first. In addition, the receiving device acknowledges each byte transferred on the bus with an acknowledge bit. Each transfer operation begins with the master device driving a start condition on the bus and ends with the master device driving a stop condition on the bus. The bus uses transitions on the data pin (SDA) while the clock is HIGH to indicate start and stop conditions. A HIGH-to-LOW transition on SDA indicates a start, and a LOW-to-HIGH transition indicates a stop. Normal data bit transitions must occur within the low time of the clock period. Figure 13 shows these conditions. The master generates the 7-bit slave address and the read/write (R/W) bit to open communication with another device and then waits for an acknowledge condition. The device holds SDA LOW during the acknowledge clock period to indicate an acknowledgment. When this occurs, the master transmits the next byte of the sequence. The address for each device is a unique 7-bit slave address plus a R/W bit (1 byte). All compatible devices share the same signals via a bidirectional bus using a wired-AND connection. The SDA and SCL signals require the use of an external pullup resistor to set the HIGH level for the bus. There is no limit on the number of bytes that the communicating devices can transmit between start and stop conditions. After transfer of the last word, the master generates a stop condition to release the bus.

TAS5421-Q1 T0035-02_SLOS814.gif Figure 13. Typical I2C Sequence

To communicate with the device, the I2C master uses addresses shown in Figure 13. Transmission of read and write data can be by single-byte or multiple-byte data transfers. Random Write

As shown in Figure 14, a single-byte data-write transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. The read/write bit determines the direction of the data transfer. For a write data transfer, the read/write bit is a 0. After receiving the correct I2C device address and the read/write bit, the device responds with an acknowledge bit. Next, the master transmits the address byte corresponding to the internal memory address being accessed. After receiving the address byte, the device again responds with an acknowledge bit. Next, the master device transmits the data byte for writing to the memory address being accessed. After receiving the data byte, the device again responds with an acknowledge bit. Finally, the master device transmits a stop condition to complete the single-byte data-write transfer.

TAS5421-Q1 T0036-05_SLOS814.gif Figure 14. Random Write Transfer Random Read

As shown in Figure 15, a single-byte data-read transfer begins with the master device transmitting a start condition followed by the I2C device address and the read/write bit. For the data-read transfer, the master device performs both a write and a following read. Initially, the master device performs a write to transfer the address byte of the internal memory address to be read. As a result, the read/write bit is a 0. After receiving the address and the read/write bit, the device responds with an acknowledge bit. In addition, after sending the internal memory address byte, the master device transmits another start condition followed by the device address and the read/write bit again. This time, the read/write bit is a 1, indicating a read transfer. After receiving the address and the read/write bit, the device again responds with an acknowledge bit. Next, the device transmits the data byte from the memory address being read. After receiving the data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the single-byte data-read transfer.

TAS5421-Q1 T0036-06_SLOS814.gif Figure 15. Random Read Transfer Sequential Read

A sequential data-read transfer is identical to a single-byte data-read transfer except that the TAS5421-Q1 transmits multiple data bytes to the master device as shown in Figure 16. Except for the last data byte, the master device responds with an acknowledge bit after receiving each data byte and automatically increments the I2C subaddress by one. After receiving the last data byte, the master device transmits a not-acknowledge followed by a stop condition to complete the transfer.

TAS5421-Q1 T0036-07_SLOS814.gif Figure 16. Sequential Read Transfer

7.4 Device Functional Modes

7.4.1 Hardware Control Pins

Three discrete hardware pins are available for real-time control and indication of device status.

  1. FAULT pin: This active-low open-drain output pin indicates the presence of a fault condition which requires the device to go into the Hi-Z mode. On assertion of this pin, the device has protected itself and the system from potential damage. The system can read the exact nature of the fault via I2C with the exception of PVDD undervoltage faults below POR, in which case the I2C bus is no longer operational.
  2. STANDBY pin: Assertion of this active-low pin sends the device goes into a complete shutdown, limiting the current draw.
  3. MUTE pin: On assertion of this active-high pin, the device is in mute mode. The output pins stop switching and audio does not pass from the input to the output. To place the device back into play mode, deassert this pin.

7.4.2 EMI Considerations

Automotive-level EMI performance depends on both careful integrated-circuit design and good system-level design. Controlling sources of electromagnetic interference (EMI) was a major consideration in all aspects of the design.

The design has minimal parasitic inductances due to the short leads on the package, which dramatically reduces the EMI that results from current passing from the die to the system PCB. The design incorporates circuitry that optimizes output transitions that cause EMI.

7.4.3 Operating Modes and Faults

The following tables list operating modes and faults.

Table 2. Operating Modes

STANDBY Hi-Z, floating Stopped Stopped
Load diagnostic DC biased Active Active
Fault and mute Hi-Z, floating Active Active
Play Switching with audio Active Active

Table 3. Faults and Actions

POR Voltage fault All Not applicable Hard mute (no ramp) Standby Self-clearing
UV or OV I2C + FAULT pin Hi-Z
Load dump(1) FAULT pin
OTSD Thermal fault Hi-Z, mute, play I2C + FAULT pin
OC fault Output channel fault Play
DC detect
Load diagnostic - short Diagnostic Hi-Z None Hi-Z, re-run diagnostics
Load diagnostic - open I2C None Clears on next diagnostic cycle
(1) Tested in accordance with ISO7637-1

7.5 Register Maps

Table 4. I2C Address

MSB 6 5 4 3 2 1 LSB
I2C write 1 1 0 1 1 0 0 0 0xD8
I2C read 1 1 0 1 1 0 0 1 0xD9

7.5.1 I2C Address Register Definitions

Table 5. I2C Address Register Definitions

0x01 R Latched fault register
0x02 R Status and load diagnostics register
0x03 R/W Control register

Table 6. Fault Register (0x01)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No protection-created faults, default value
1 Reserved
1 Reserved
1 A load-diagnostics fault has occurred.
1 Overcurrent shutdown has occurred.
1 PVDD undervoltage has occurred.
1 PVDD overvoltage has occurred.
1 DC offset protection has occurred.
1 Overtemperature shutdown has occurred.

Table 7. Status and Load Diagnostic Register (0x02)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 0 0 0 0 0 0 0 No speaker-diagnostic-created faults, default value
1 Output short to PVDD is present.
1 Output short to ground is present.
1 Open load is present.
1 Shorted load is present.
1 In a fault condition
1 Performing load diagnostics
1 In mute mode
1 In play mode

Table 8. Control Register (0x03)

D7 D6 D5 D4 D3 D2 D1 D0 FUNCTION
0 1 1 1 1 0 0 0 26-dB gain, switching frequency set to 400 kHz , SpeakerGuard protection circuitry disabled
1 Switching frequency set to 500 khz
1 1 - Reserved
1 1 0 SpeakerGuard protection circuitry set to 14-V peak output
1 0 1 SpeakerGuard protection circuitry set to 11.8-V peak output
1 0 0 SpeakerGuard protection circuitry set to 9.8-V peak output
0 1 1 SpeakerGuard protection circuitry set to 8.4-V peak output
0 1 0 SpeakerGuard protection circuitry set to 7-V peak output
0 0 1 SpeakerGuard protection circuitry set to 5.9-V peak output
0 0 0 SpeakerGuard protection circuitry set to 5-V peak output
0 0 Gain set to 20 dB
1 0 Gain set to 32 dB
1 1 Gain set to 36 dB