SLOS814D March   2014  – September 2016 TAS5421-Q1


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements for I2C Interface Signals
    7. 6.7 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Audio Input and Preamplifier
      2. 7.3.2 Pulse-Width Modulator (PWM)
      3. 7.3.3 Gate Drive
      4. 7.3.4 Power FETs
      5. 7.3.5 Load Diagnostics
      6. 7.3.6 Protection and Monitoring
      7. 7.3.7 I2C Serial Communication Bus
        1. I2C Bus Protocol
        2. Random Write
        3. Random Read
        4. Sequential Read
    4. 7.4 Device Functional Modes
      1. 7.4.1 Hardware Control Pins
      2. 7.4.2 EMI Considerations
      3. 7.4.3 Operating Modes and Faults
    5. 7.5 Register Maps
      1. 7.5.1 I2C Address Register Definitions
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
        1. Amplifier Output Filtering
        2. Amplifier Output Snubbers
        3. Bootstrap Capacitors
        4. Analog Audio Input Filter
      2. 8.2.2 Detailed Design Procedure
        1. Unused Pin Connections
          1. MUTE Pin
          2. STANDBY Pin
          3. I2C Pins (SDA and SCL)
          4. Terminating Unused Outputs
          5. Using a Single-Ended Audio Input
      3. 8.2.3 Application Curves
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
      1. 10.2.1 Top Layer
      2. 10.2.2 Second Layer - Signal Layer
      3. 10.2.3 Third Layer - Power Layer
      4. 10.2.4 Bottom Layer - Ground Layer
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Third-Party Products Disclaimer
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 Community Resource
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

10 Layout

10.1 Layout Guidelines

The EVM layout optimizes for thermal dissipation and EMC performance. The TAS5421-Q1 device has a thermal pad down, and good thermal conduction and dissipation require adequate copper area. Layout also affects EMC performance. TAS5421Q1EVM illustrations form the basis for the layout discussions.

10.2 Layout Examples

10.2.1 Top Layer

The red boxes around number 1 are the copper ground on the top layer. Soldered directly to the thermal pad, the ground is the first significant thermal dissipation required. There are vias that go to the other layers for further thermal relief, but vias have high thermal resistance. TI recommends that use of the top layer be mostly for thermal dissipation. A further recommendation is short routes from output pins to the second-order LC filter for EMC suppression. The number 2 arrow indicates these short routes. The shorter the distance, the less EMC radiates. A short route from the PVDD pin to the LC filter from the battery or power source, as indicated by the number 3 arrow, also improves EMC suppression. The red box around number 4 indicates the ground plane that is common to both OUTP and OUTN. Place the capacitors of the LC filter in the common ground plane to help with common-mode noise and short ground loops.

TAS5421-Q1 Layer1_SLOS814.png Figure 18. Top Layer

10.2.2 Second Layer – Signal Layer

If possible, route the I2C and the positive and negative input traces close together and cover with ground plane, keeping the signals from noise.

TAS5421-Q1 Layer2_SLOS814.png Figure 19. Signal Layer

10.2.3 Third Layer – Power Layer

There is no requirement for a power plane, but TI recommends a wide single PVDD trace to keep the switching noise to a minimum and provide enough current to the device. The wide trace provides a low-impedance path from the power source to the PVDD pin and from the GND pin to the source return. Suppression of switching noise (ripple voltage) on both the positive and return (ground) paths requires a low impedance.

TAS5421-Q1 Layer3_SLOS814.png Figure 20. Power Layer

10.2.4 Bottom Layer – Ground Layer

The device has an exposed thermal pad on the bottom side for improved thermal performance. Conducting heat from the thermal pad to other layers requires thermal vias. Because the bottom layer is the secondary heat exchange surface to ambient, the thermal vias area must have low thermal resistance, that is, no signal vias or traces that can increase thermal resistance from the thermal vias to the bottom copper.

TAS5421-Q1 Layer4_SLOS814.png Figure 21. Bottom Layer