SLASEA5C March   2016  – May 2017 TAS5753MD


  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Pin Configuration and Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Characteristics
    5. 6.5  Electrical Characteristics
    6. 6.6  Speaker Amplifier Characteristics in All Modes
    7. 6.7  Speaker Amplifier Characteristics in Stereo Bridge Tied Load (BTL) Mode
    8. 6.8  Speaker Amplifier Characteristics in Stereo Post-Filter Parallel Bridge Tied Load (Post-Filter PBTL) Mode
    9. 6.9  Headphone Amplifier and Line Driver Characteristics
    10. 6.10 Protection Circuitry Characteristics
    11. 6.11 I²C Interface Timing Requirements
    12. 6.12 Serial Audio Port Timing Requirements
    13. 6.13 Typical Electrical Power Consumption
    14. 6.14 Typical Characteristics
      1. 6.14.1 Typical Characteristics - BTL Mode
      2. 6.14.2 Typical Characteristics - PBTL Mode
      3. 6.14.3 Typical Characteristics - Headphone Amplifier
      4. 6.14.4 Typical Characteristics - Line Driver
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Audio Signal Processing Overview
    4. 7.4 Feature Description
      1. 7.4.1 Clock, Autodetection, and PLL
      2. 7.4.2 PWM Section
      3. 7.4.3 PWM Level Meter
      4. 7.4.4 Automatic Gain Limiter (AGL)
      5. 7.4.5 Headphone/Line Amplifier
      6. 7.4.6 Fault Indication
      7. 7.4.7 SSTIMER Pin Functionality
      8. 7.4.8 Device Protection System
        1. Overcurrent (OC) Protection With Current Limiting
        2. Overtemperature Protection
        3. Undervoltage Protection (UVP) and Power-On Reset (POR)
    5. 7.5 Device Functional Modes
      1. 7.5.1 Serial Audio Port Operating Modes
      2. 7.5.2 Communication Port Operating Modes
      3. 7.5.3 Speaker Amplifier Modes
        1. Stereo Mode
        2. Mono Mode
    6. 7.6 Programming
      1. 7.6.1 I²C Serial Control Interface
        1. General I²C Operation
        2. I²C Slave Address
          1. I²C Device Address Change Procedure
        3. Single- and Multiple-Byte Transfers
        4. Single-Byte Write
        5. Multiple-Byte Write
        6. Single-Byte Read
        7. Multiple-Byte Read
      2. 7.6.2 Serial Interface Control and Timing
        1. Serial Data Interface
        2. I²S Timing
        3. Left-Justified
        4. Right-Justified
      3. 7.6.3 26-Bit 3.23 Number Format
    7. 7.7 Register Maps
      1. 7.7.1 Register Summary
      2. 7.7.2 Detailed Register Descriptions
        1.  Clock Control Register (0x00)
        2.  Device ID Register (0x01)
        3.  Error Status Register (0x02)
        4.  System Control Register 1 (0x03)
        5.  Serial Data Interface Register (0x04)
        6.  System Control Register 2 (0x05)
        7.  Soft Mute Register (0x06)
        8.  Volume Registers (0x07, 0x08, 0x09)
        9.  Volume Configuration Register (0x0E)
        10. Modulation Limit Register (0x10)
        11. Interchannel Delay Registers (0x11, 0x12, 0x13, and 0x14)
        12. PWM Shutdown Group Register (0x19)
        13. Start/Stop Period Register (0x1A)
        14. Oscillator Trim Register (0x1B)
        15. BKND_ERR Register (0x1C)
        16. Input Multiplexer Register (0x20)
        17. PWM Output MUX Register (0x25)
        18. AGL Control Register (0x46)
        19. PWM Switching Rate Control Register (0x4F)
        20. Bank Switch and EQ Control (0x50)
  8. Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 External Component Selection Criteria
        1. Component Selection Impact on Board Layout, Component Placement, and Trace Routing
        2. Amplifier Output Filtering
    2. 8.2 Typical Applications
      1. 8.2.1 Stereo Bridge Tied Load Application
        1. Design Requirements
        2. Detailed Design Procedure
          1. Component Selection and Hardware Connections
          2. Control and Software Integration
          3. I²C Pullup Resistors
          4. Digital I/O Connectivity
          5. Recommended Startup and Shutdown Procedures
            1. Start-Up Sequence
            2. Normal Operation
            3. Shutdown Sequence
            4. Power-Down Sequence
        3. Application Performance Plots
      2. 8.2.2 Mono Parallel Bridge Tied Load Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Performance Plots
      3. 8.2.3 Stereo BTL Configuration with Headphone and Line Driver Amplifier Application
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Performance Plots
      4. 8.2.4 Mono Parallel Bridge-Tied Load Configuration with Headphone and Line Driver Amplifier
        1. Design Requirements
        2. Detailed Design Procedure
        3. Application Performance Plots
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Decoupling Capacitors
      2. 10.1.2 Thermal Performance and Grounding
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Community Resources
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Power Supply Recommendations

To facilitate system design, the TAS5753MD device requires only a 3.3-V supply in addition to the PVDD power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.

To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRP_x), and power-stage supply pins (PVDD). The gate-drive voltage (GVDD_REG) is derived from the PVDD voltage. Place all decoupling capacitors as close to their associated pins as possible. In addition, avoid inductance between the power-supply pins and the decoupling capacitors.

For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRP_x) to the power-stage output pin (AMP_OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. The capacitors shown in Typical Applications ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.

Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, each PVDD pin should be decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.

The TAS5753MD device is fully protected against erroneous power-stage turn-on due to parasitic gate charging.