SLASEA5C March 2016 – May 2017 TAS5753MD
To facilitate system design, the TAS5753MD device requires only a 3.3-V supply in addition to the PVDD power-stage supply. An internal voltage regulator provides suitable voltage levels for the gate drive circuitry. Additionally, all circuitry requiring a floating voltage supply, e.g., the high-side gate drive, is accommodated by built-in bootstrap circuitry requiring only a few external capacitors.
To provide good electrical and acoustical characteristics, the PWM signal path for the output stage is designed as identical, independent half-bridges. For this reason, each half-bridge has separate bootstrap pins (BSTRP_x), and power-stage supply pins (PVDD). The gate-drive voltage (GVDD_REG) is derived from the PVDD voltage. Place all decoupling capacitors as close to their associated pins as possible. In addition, avoid inductance between the power-supply pins and the decoupling capacitors.
For a properly functioning bootstrap circuit, a small ceramic capacitor must be connected from each bootstrap pin (BSTRP_x) to the power-stage output pin (AMP_OUT_X). When the power-stage output is low, the bootstrap capacitor is charged through an internal diode connected between the gate-drive regulator output pin (GVDD_REG) and the bootstrap pin. When the power-stage output is high, the bootstrap capacitor potential is shifted above the output potential and thus provides a suitable voltage supply for the high-side gate driver. The capacitors shown in Typical Applications ensure sufficient energy storage, even during minimal PWM duty cycles, to keep the high-side power-stage FET (LDMOS) fully turned on during the remaining part of the PWM cycle.
Special attention should be paid to the power-stage power supply; this includes component selection, PCB placement, and routing. As indicated, each half-bridge has independent power-stage supply pins (PVDD). For optimal electrical performance, EMI compliance, and system reliability, each PVDD pin should be decoupled with a 100-nF, X7R ceramic capacitor placed as close as possible to each supply pin.
The TAS5753MD device is fully protected against erroneous power-stage turn-on due to parasitic gate charging.