SLVSKC7 September   2026 TAS5832

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Requirements
    7. 5.7 Typical Characteristics
      1. 5.7.1 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      2. 5.7.2 Bridge Tied Load (BTL) Configuration Curves with 1SPW Modulation
      3. 5.7.3 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
      4. 5.7.4 Parallel Bridge Tied Load (PBTL) Configuration With 1SPW Modulation
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Supplies
      2. 6.3.2 Device Clocking
      3. 6.3.3 Serial Audio Port – Clock Rates
      4. 6.3.4 Clock Halt Auto-recovery
      5. 6.3.5 Sample Rate on the Fly Change
      6. 6.3.6 Serial Audio Port - Data Formats and Bit Depths
    4. 6.4 Device Functional Modes
      1. 6.4.1 Software Control
      2. 6.4.2 Speaker Amplifier Operating Modes
        1. 6.4.2.1 BTL Mode
        2. 6.4.2.2 PBTL Mode
      3. 6.4.3 Low EMI Modes
        1. 6.4.3.1 Spread Spectrum
        2. 6.4.3.2 Channel to Channel Phase Shift
        3. 6.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 6.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 6.4.3.3.2 Phase Synchronization With GPIO
      4. 6.4.4 Thermal Foldback
      5. 6.4.5 Device State Control
      6. 6.4.6 Device Modulation
        1. 6.4.6.1 BD Modulation
        2. 6.4.6.2 1SPW Modulation
        3. 6.4.6.3 Hybrid Modulation
      7. 6.4.7 Programming and Control
        1. 6.4.7.1 I2C Serial Communication Bus
        2. 6.4.7.2 Hardware Control Mode
        3. 6.4.7.3 I2C Target Address
          1. 6.4.7.3.1 Random Write
          2. 6.4.7.3.2 Sequential Write
          3. 6.4.7.3.3 Random Read
          4. 6.4.7.3.4 Sequential Read
          5. 6.4.7.3.5 DSP Memory Book, Page and BQ update
          6. 6.4.7.3.6 Checksum
            1. 6.4.7.3.6.1 Cyclic Redundancy Check (CRC) Checksum
            2. 6.4.7.3.6.2 Exclusive or (XOR) Checksum
        4. 6.4.7.4 Control via Software
          1. 6.4.7.4.1 Startup Procedures
          2. 6.4.7.4.2 Shutdown Procedures
        5. 6.4.7.5 Protection and Monitoring
          1. 6.4.7.5.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 6.4.7.5.2 Overcurrent Shutdown (OCSD)
          3. 6.4.7.5.3 DC Detect Error
          4. 6.4.7.5.4 Overtemperature Shutdown (OTSD)
          5. 6.4.7.5.5 PVDD Overvoltage and Undervoltage Error
          6. 6.4.7.5.6 PVDD Drop Detection
          7. 6.4.7.5.7 Clock Fault
  8. 7 Register Maps
    1. 7.1 Registers
  9. 8 Application and Implementation
    1. 8.1 Typical Applications
      1. 8.1.1 2.0 (Stereo BTL) System
      2. 8.1.2 Mono (PBTL) Systems
    2. 8.2 Layout
      1. 8.2.1 Layout Guidelines
        1. 8.2.1.1 General Guidelines for Audio Amplifiers
        2. 8.2.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      2. 8.2.2 Layout Example
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 DVDD Supply
      2. 8.3.2 PVDD Supply
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
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Thermal pad, mechanical data (Package|Pins)
Orderable Information

4 Pin Configuration and Functions

TAS5832 DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View Figure 4-1 DAD (TSSOP) Package, 32-Pin PadUp, Software Mode, Top View
Table 4-1 Pin Functions - Software Mode
PIN TYPE(1) DESCRIPTION
NAME NO.
ADR 13 AI A table of resistor value (Pull down to GND) decides the device I2C address. See Section 6.4.7.3.
AGND 1 G Analog ground.
AVDD 2 P Internally regulated 5V analog supply voltage. This pin must not be used to drive external devices.
BCLK 8 DI Bit clock for the digital signal that is active on the input data line of the serial data port.
BST_A- 24 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_A+ 20 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
BST_B- 25 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
BST_B+ 29 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
DGND 16 G Digital ground.
DVDD 15 P 3.3V or 1.8V digital power supply.
GPIO0 12 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x63h). Can be configured to be open drain output or push-pull output.
GPIO1 11 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x61h). Can be configured to be open drain output or push-pull output.
GPIO2 10 DI/O General-purpose input/output, function of this pin can be programmed by register (Register Address 0x60h and 0x62h). Can be configured to be open drain output or push-pull output.
GVDD 3 P Gate drive internal regulator output. This pin must not be used to drive external devices.
LRCLK 9 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
OUT_A- 23 O Negative pin for differential speaker amplifier output A.
OUT_A+ 19 O Positive pin for differential speaker amplifier output A.
OUT_B- 26 O Negative pin for differential speaker amplifier output B.
OUT_B+ 30 O Positive pin for differential speaker amplifier output B.
PDN 4 DI Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
PGND 21, 22, 27, 28 G Ground reference for power device circuitry. Connect this pin to system ground.
PowerPAD™ P Ground, connect to grounded heat sink for best system performance.
PVDD 17, 18, 31, 32 P PVDD voltage input.
SCL 5 DI I2C serial control clock input.
SDA 6 DI/O I2C serial control data interface input/output.
SDIN 7 DI Data line to the serial data port.
VR_DIG 14 P Internally regulated 1.5V digital supply voltage. This pin must not be used to drive external devices.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), PO = Positive output, NO = Negative output, P = Power, G = Ground (0V)
TAS5832 DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode, Top View Figure 4-2 DAD (TSSOP) Package, 32-Pin PadUp, Hardware Mode, Top View
Table 4-2 Pin Functions - Hardware Mode
PIN TYPE(1) DESCRIPTION
NAME NO.
AGND 1 G Analog ground.
AVDD 2 P Internally regulated 5V analog supply voltage. This pin must not be used to drive external devices.
BCLK 8 DI Bit clock for the digital signal that is active on the input data line of the serial data port.
BST_A- 24 P Connection point for the OUT_A- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A-.
BST_A+ 20 P Connection point for the OUT_A+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_A+.
BST_B- 25 P Connection point for the OUT_B- bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B-.
BST_B+ 29 P Connection point for the OUT_B+ bootstrap capacitor which is used to create a power supply for the high-side gate drive for OUT_B+.
DGND 16 G Digital ground.
DVDD 15 P 3.3V or 1.8V digital power supply.
FAULT 11 DO Fault terminal,which is pulled LOW when an internal fault occurs.
GVDD 3 P Gate drive internal regulator output. This pin must not be used to drive external devices.
HW_MODE 13 AI Connect to DVDD directly to verify device enters into Hardware Control Mode.
HW_SEL0 5 DI Analog gain and BTL/PBTL mode selection in Hardware Mode . Pull up to DVDD or Pull down to ground with different resistor. See Section 6.4.7.2.
HW_SEL1 6 DI PWM Switching Frequency and Spread Spectrum Enable/Disable selection in Hardware Mode. Pull up to DVDD or Pull down to ground with different resistor. See Section 6.4.7.2.
LRCLK 9 DI Word select clock for the digital signal that is active on the serial port's input data line. In I2S, LJ and RJ, this corresponds to the left channel and right channel boundary. In TDM mode, this corresponds to the frame sync boundary.
MUTE 10 DI Speaker amplifier Mute. Which must be pulled low (connect to DGND) to MUTE the device and pulled high (connected to DVDD) to exit MUTE state. In Mute state, device output keep in Hi-Z state.
OUT_A- 23 O Negative pin for differential speaker amplifier output A.
OUT_A+ 19 O Positive pin for differential speaker amplifier output A.
OUT_B- 26 O Negative pin for differential speaker amplifier output B.
OUT_B+ 30 O Positive pin for differential speaker amplifier output B.
PD_DET 12 DO PVDD Drop detection, which is pulled LOW when the PVDD drop below 8V.
PDN 4 DI Power down, active-low. PDN place the amplifier in Shutdown, turn off all internal regulators.
PGND 21, 22, 27, 28 G Ground reference for power device circuitry. Connect this pin to system ground.
PowerPAD™ P Ground, connect to grounded heat sink for best system performance.
PVDD 17, 18, 31, 32 P PVDD voltage input.
SDIN 7 DI Data line to the serial data port.
VR_DIG 14 P Internally regulated 1.5V digital supply voltage. This pin must not be used to drive external devices.
(1) AI = Analog input, AO = Analog output, DI = Digital Input, DO = Digital Output, DI/O = Digital Bi-directional (input and output), PO = Positive output, NO = Negative output, P = Power, G = Ground (0V)