SCPS253C January   2014  – September 2019 TCA5013

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Handling Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics—Power Supply and ESD
    6. 6.6  Electrical Characteristics—Card VCC
    7. 6.7  Electrical Characteristics—Card RST
    8. 6.8  Electrical Characteristics—Card CLK
    9. 6.9  Electrical Characteristics—Card Interface IO, C4 and C8
    10. 6.10 Electrical Characteristics—PRES
    11. 6.11 Electrical Characteristics—IOMC1 and IOMC2
    12. 6.12 Electrical Characteristics—CLKIN1 and CLKIN2
    13. 6.13 Electrical Characteristics—A0 and SHDN
    14. 6.14 Electrical Characteristics—INT
    15. 6.15 Electrical Characteristics—GPIO
    16. 6.16 Electrical Characteristics—SDA and SCL
    17. 6.17 Electrical Characteristics—Fault Condition Detection
    18. 6.18 I2C Interface Timing Requirements
    19. 6.19 I2C Interface Timing Characteristics
    20. 6.20 Synchronous Type 1 Card Activation Timing Characteristics
    21. 6.21 Synchronous Type 2 Card Activation Timing Characteristics
    22. 6.22 Card Deactivation Timing Characteristics
    23. 6.23 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Card Interface Modules
      2. 8.3.2 SAM Card Interface Modules
      3. 8.3.3 User Card Interface Module
      4. 8.3.4 Clock Division and Multiplexing
      5. 8.3.5 IO Multiplexing
      6. 8.3.6 GPIO Operation
      7. 8.3.7 Power Management Features
      8. 8.3.8 ESD Protection
      9. 8.3.9 I2C interface
    4. 8.4 Device Functional Modes
      1. 8.4.1  Power Off Mode
      2. 8.4.2  Shutdown Mode
      3. 8.4.3  Standby Mode
      4. 8.4.4  Active Mode
        1. 8.4.4.1 User Card Operating Mode Selection
        2. 8.4.4.2 Synchronous Type 1 Operating Mode
        3. 8.4.4.3 Synchronous Type 2 Operating Mode
        4. 8.4.4.4 Manual Operating Mode
        5. 8.4.4.5 Asynchronous Operating Mode
        6. 8.4.4.6 Warm Reset Sequence
        7. 8.4.4.7 Deactivation Sequence
      5. 8.4.5  User Card Insertion / Removal Detection
      6. 8.4.6  IO Operation
        1. 8.4.6.1 IO Switching Control
        2. 8.4.6.2 IO Rise Time and Fall Time control
        3. 8.4.6.3 Current Limiting on IO Pin
      7. 8.4.7  CLK Operation
        1. 8.4.7.1 CLK Switching
        2. 8.4.7.2 CLK Rise Time and Fall Time Control
        3. 8.4.7.3 Current Limiting On CLK Pin
      8. 8.4.8  RST Operation
        1. 8.4.8.1 Current Limiting On RST
      9. 8.4.9  Interrupt Operation
        1. 8.4.9.1  Card Insertion And Removal
        2. 8.4.9.2  Over Current Fault
        3. 8.4.9.3  Supervisor Fault
        4. 8.4.9.4  Over Temperature Fault
        5. 8.4.9.5  EARLY Fault
        6. 8.4.9.6  MUTE Fault
        7. 8.4.9.7  Synchronous Activation Complete
        8. 8.4.9.8  VCC Ramp Fault
        9. 8.4.9.9  GPIO Input State Transition
        10. 8.4.9.10 POR Interrupt
      10. 8.4.10 Power Management
        1. 8.4.10.1 Voltage Supervisor
        2. 8.4.10.2 DC-DC Boost
        3. 8.4.10.3 LDOs and Load Transient Response
    5. 8.5 Programming
      1. 8.5.1 I2C Interface Operation
        1. 8.5.1.1 I2C Read and Write Procedures
        2. 8.5.1.2 I2C Address Configuration
    6. 8.6 Register Maps
      1. 8.6.1 Memory Map
        1. Table 12. 91
        2. Table 13. 92
        3. Table 14. 93
        4. Table 15. 94
        5. Table 16. 95
        6. Table 17. 96
        7. Table 18. 97
        8. Table 19. 98
        9. Table 20. 99
        10. Table 21. 100
        11. Table 22. 101
        12. Table 23. 102
        13. Table 24. 103
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 IO Pin Fall Time Setting
        2. 9.2.2.2 CLK Pin Rise Time And Fall Time Settings
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
    1. 10.1 Power-On-Reset
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 DC-DC Boost Layout Recommendation
      2. 11.1.2 Card Interface Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Trademarks
    2. 12.2 Electrostatic Discharge Caution
    3. 12.3 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

CLK Switching

The CLK output on each of the smartcard interfaces can be controlled by the corresponding clock settings register (Reg 0x02 for user card, Reg 0x12 for SAM1, Reg 0x22 for SAM2, Reg 0x32 for SAM3). The CLKIN1 pin is dedicated for the user card interface while The CLKIN2 is shared between the SAM interfaces. The clock settings register allows the CLK output to be configured in one of 4 different modes.

  1. CLK 0 mode - The CLK output of the card interface is static low.
  2. CLK 1 mode - The CLK output of the card interface is static high.
  3. CLK div mode - The CLK output is a divided down frequency of the CLKIN1 or CLKIN2 frequency. Bit [4:2] of clock settings register defines the division ratio.
  4. Internal CLK mode - The CLK output is at a fixed frequency (~1.2 MHz) based off the internal oscillator.

The allowable changes in CLK output can vary depending on the mode in which the interface has been activated. In asynchronous mode (see Asynchronous Operating Mode), The CLK output can be dynamically switched from one state to another. Table 8 shows the permitted frequency transitions on CLK pin in asynchronous mode. Any I2C command that attempts to switch the CLK frequency outside of these state transitions can result in the change not happening on the output or other unpredictable behavior that could cause device to lock up. If the device enters such a locked state, it can be reset by toggling SHDN pin.

Table 8. Permitted CLK Switching Operations in Asynchronous Mode

FROM TO
Internal CLK CLK div Permitted
Internal CLK CLK 0 Not Permitted
Internal CLK CLK 1 Not Permitted
CLK div Internal CLK Permitted
CLK div CLK 0 Permitted
CLK div CLK 1 Permitted
CLK 0 CLK div Permitted
CLK 0 Internal CLK Not Permitted
CLK 0 CLK1 Not Permitted
CLK 1 CLK div Permitted
CLK 1 Internal CLK Not Permitted
CLK 1 CLK 0 Not Permitted

When command sets the device in Internal clock mode or CLK 0 mode or CLK 1 mode, the division ratio is locked out, that is, when an I2C transaction that sets either one of the bits [7:5] of the card clock settings register to 1, the remaining bits in the register (bit [4:2]) will not not be updated. It is to be noted that an asynchronous activation cannot be performed with the internal clock. At the start of the asynchronous activation, if the internal CLK mode is selected in the clock settings register, then the device shall begin activation based on divide ratio defined by bit [4:2] of clock settings register. After the activation is completed, the CLK output will switch to Internal CLK mode. When switching to/from a CLK div mode from/to CLK 0 mode or CLK 1 mode, the device waits for the input clock (CLKIN1 or CLKIN2) phase to match the static level it will switch to/from and then makes the transition to ensure that no partial pulses or glitches are seen on the output clock. Similarly, when switching from one division ratio to another the change happens on the rising clock edges to ensure no glitch on the output. Figure 15 shows how the change in divide ratio is seen on the CLK pin.

TCA5013 fig019_SCPS253.gifFigure 15. CLK Divide Ratio Change on Card CLK Output

When switching from CLK divide mode to the Internal CLK mode, the device waits for the edges of the internal and external clock to line up (fall within ~10 ns of each other) and makes the switch on that edge. If the external clock is close to an exact harmonic of 1.2 MHz, there could be a situation where the rising edges of the two clocks take very long (milliseconds or seconds) to line up and this would mean the frequency switch at the output would happen long after the I2C command to make the switch is issued. The CLKSW bit (bit [3]) in the card interface status register (Reg 0x01 for user card, Reg 0x11 for SAM1, Reg 0x21 for SAM2, Reg 0x31for SAM3) is set when the internal clock frequency is seen on the CLK pin.

TCA5013 fig020_SCPS253.gifFigure 16. Output CLK Frequency Transition When Switching From External Clock to Internal Clock

In CLK divide mode, when CLKIN/2, CLKIN/4 or CLKIN/8 division ratios are used, the output duty cycle is not affected by the duty cycle of the input clock on CLKIN. When the CLKIN/1 and CLKIN/5 division ratios are used, the output clock duty cycle is a function of the CLKIN1/CLKIN2 duty cycle. For CLKIN/1 the output duty cycle will be equal to the input duty cycle. For CLKIN/5 the output CLK duty cycle is given by (n+2) / 5, where n is the duty cycle of the input clk; for example, if the input clk has a 40% duty cycle (n = 0.4) the CLKIN/5 output will have a (0.4+2) / 5 = 0.48 or 48% duty cycle. In addition to asynchronous mode, the user card interface can also operate in synchronous mode (see Synchronous Type 1 Operating Mode and Synchronous Type 2 Operating Mode).When in synchronous mode the user card CLK pin output is controlled by CLK_ENABLE_SYNC (bit [2], Reg 0x09) in addition to the clock settings register. Figure 17 shows a simplified logical representation of the user card clock muxing circuit.

TCA5013 fig021_SCPS253.gifFigure 17. Clock Muxing Logic in Synchronous Mode

Unlike all the other bits that control the CLK, the CLK_ENABLE_SYNC can cause the CLK state to transition instantly. This means that when switching from a static level to a toggling CLK (or vice-versa), there can be partial pulses (glitches) on the CLK output when CLK_ENABLE_SYNC is switched. In sync mode, the CLK output can be switched directly from one static level to another, by using the CLK settings register (when CLK_SYNC_ENABLE = 0).

Table 9. Card CLK Truth Table in Synchronous Mode

CLK_ENABLE_SYNC CARD CLOCK SETTINGS REGISTER CARD CLK OUTPUT
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2
0 X 1 X X X X 1
0 X 0 X X X X 0
1 X X X X X X CLKIN1