In a 4-layer board design, the recommended layer stack order from top to bottom is: signal, ground, power and signal.
Bypass capacitors should be placed in close proximity to the VDD pin.
The length of the START and STOP traces from the TDC7200 to the stopwatch/MCU should be matched to prevent uneven signal delays. Also, avoid unnecessary via-holes on these traces and keep the routing as short/direct as possible to minimize parasitic capacitance on the PCB.
Route the SPI signal traces close together. Place a series resistor at the source of DOUT (close to the TDC7200) and series resistors at the sources of DIN, SCLK, and CSB (close to the master MCU).