SLOS375A August   2014  – September 2014 THS4541

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Device Family Comparison
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 Handling Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics: Vs+ - Vs- = 5 V
    6. 7.6 Electrical Characteristics: Vs+ - Vs- = 3 V
    7. 7.7 Typical Characteristics: 5-V Single Supply
    8. 7.8 Typical Characteristics: 3-V Single Supply
    9. 7.9 Typical Characteristics: 3-V to 5-V Supply Range
  8. 8 Parameter Measurement Information
    1. 8.1 Example Characterization Circuits
    2. 8.2 Frequency-Response Shape Factors
    3. 8.3 I/O Headroom Considerations
    4. 8.4 Output DC Error and Drift Calculations and the Effect of Resistor Imbalances
    5. 8.5 Noise Analysis
    6. 8.6 Factors Influencing Harmonic Distortion
    7. 8.7 Driving Capacitive Loads
    8. 8.8 Thermal Analysis
  9. 9 Detailed Description
    1. 9.1 Overview
      1. 9.1.1 Terminology and Application Assumptions
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Differential I/O
      2. 9.3.2 Power-Down Control Pin (PD)
        1. 9.3.2.1 Operating the Power Shutdown Feature
      3. 9.3.3 Input Overdrive Operation
    4. 9.4 Device Functional Modes
      1. 9.4.1 Operation from Single-Ended Sources to Differential Outputs
        1. 9.4.1.1 AC-Coupled Signal Path Considerations for Single-Ended Input to Differential Output Conversion
        2. 9.4.1.2 DC-Coupled Input Signal Path Considerations for Single-Ended to Differential Conversion
        3. 9.4.1.3 Resistor Design Equations for the Single-Ended to Differential Configuration of the FDA
        4. 9.4.1.4 Input Impedance for the Single-Ended to Differential FDA Configuration
      2. 9.4.2 Differential-Input to Differential-Output Operation
        1. 9.4.2.1 AC-Coupled, Differential-Input to Differential-Output Design Issues
        2. 9.4.2.2 DC-Coupled, Differential-Input to Differential-Output Design Issues
  10. 10Application And Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Applications
      1. 10.2.1 Designing Attenuators
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Interfacing to High-Performance ADCs
        1. 10.2.2.1 Design Requirements
        2. 10.2.2.2 Detailed Design Procedure
        3. 10.2.2.3 Application Curve
  11. 11Power-Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Third-Party Products Disclaimer
      2. 13.1.2 Development Support
        1. 13.1.2.1 TINA Simulation Model Features
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Fully Differential Amplifier (FDA) Architecture
  • Bandwidth: 500 MHz (G = 2 V/V)
  • Gain Bandwidth Product: 850 MHz
  • Slew Rate: 1500 V/µs
  • HD2: –95 dBc at 10 MHz (2 VPP, RL = 500 Ω)
  • HD3: –90 dBc at 10 MHz (2 VPP, RL = 500 Ω)
  • Input Voltage Noise: 2.2 nV/Hz (f > 100 kHz)
  • Low offset drift: ±0.5 µV/°C (typ)
  • Negative Rail Input (NRI)
  • Rail-to-Rail Output (RRO)
  • Robust Operation for Rload ≥ 50 Ω
  • Output Common-Mode Control
  • Power Supply:
    • Single-Supply Voltage Range: 2.7 V to 5.4 V
    • Split-Supply Voltage Range: ±1.35 V to ±2.7 V
    • Quiescent Current: 10.1 mA (5-V Supply)
  • Power-Down Capability: 2 µA (typ)

2 Applications

  • Low-Power, High-Performance ADC Driver
    • SAR, ΔΣ, and Pipeline
  • Low Power, High Performance
    (DC or AC Coupled)
    • Single-Ended to Differential Amplifier
    • Differential to Differential Amplifier
  • Differential Active Filters
  • Differential Transimpedance for DAC Outputs
  • DC- or AC-Coupled Interface to the ADC3xxx Family of Low-Power, High-Performance ADCs
  • Pin-Compatible to ADA4932-1 (VQFN-16)

3 Description

The THS4541 is a low-power, voltage-feedback, fully differential amplifier (FDA) with an input common-mode range below the negative rail, and rail-to-rail output. Designed for low-power data acquisition systems where high density is critical in a high-performance analog-to-digital converter (ADC) or digital-to-analog converter (DAC) interface design.

The THS4541 features the negative-rail input required when interfacing a dc-coupled, ground-centered, source signal. This negative-rail input, with rail-to-rail output, allows for easy interface between single-ended, ground-referenced, bipolar signal sources and a wide variety of successive approximation register (SAR), delta-sigma (ΔΣ), or pipeline ADCs using only a single +2.7-V to +5.4-V power supply.

The THS4541 is characterized for operation over the wide temperature range of –40°C to 125°C available in 16-pin VQFN and 10-pin WQFN packages.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)
THS4541 VQFN (16) 3.00 mm × 3.00 mm
WQFN (10) 2.00 mm × 2.00 mm
  1. For all available packages, see the package option addendum at the end of the data sheet.

Simplified Schematic

ac_coupled_gain_los375.gif

Single to Differential Gain of 2, 2-VPP Output

D013_SLOS375.gif