SLVSLX7A April   2026  – September 2026

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Host Serial Interface DC Characteristics
    7. 5.7 Host Serial Interface AC Characteristics
    8. 5.8 Power Consumption
    9. 5.9 Typical Characteristics
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Counter, Latches, Clock Multiplier
      2. 6.3.2 Channels, Interpolator
      3. 6.3.3 FIFO
      4. 6.3.4 Calibration, ALU, Tag, Shifter
      5. 6.3.5 Serial Interface, Temperature, Overhead
    4. 6.4 Device Functional Modes
      1. 6.4.1 Serial-Results Interface
      2. 6.4.2 Result-Interface Clock
      3. 6.4.3 DDR Mode
      4. 6.4.4 Output Interface Throughput
      5. 6.4.5 Counter Range
        1. 6.4.5.1 Preconditioning Holdoff Delay Time
        2. 6.4.5.2 Arming Conditions
      6. 6.4.6 Resister Map Descriptions for All Channels and Central Register
    5. 6.5 Programming
      1. 6.5.1 Host Processor Bus Interface
        1. 6.5.1.1  Serial Interface
        2. 6.5.1.2  Read vs Write Cycle
        3. 6.5.1.3  Parallel (Broadcast) Write
        4. 6.5.1.4  Address
        5. 6.5.1.5  Data
        6. 6.5.1.6  Reset
        7. 6.5.1.7  Chip ID
        8. 6.5.1.8  Read Operations
        9. 6.5.1.9  Write Operations
        10. 6.5.1.10 Write Operations to Multiple Destinations
      2. 6.5.2 Serial-Results Interface and ALU
        1. 6.5.2.1 Event Latches
        2. 6.5.2.2 FIFO
        3. 6.5.2.3 Result-Interface Operation
        4. 6.5.2.4 Serial Results Latency
        5. 6.5.2.5 TMU Calibration
        6. 6.5.2.6 Temperature Sensor
  8. 7 Registers
    1. 7.1 Register Maps
      1. 7.1.1 Register Address Space
      2. 7.1.2 Register Map Detail
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedures
        1. 8.2.2.1 Time Measurement
        2. 8.2.2.2 Output Clock to Data/Strobe Phasing
        3. 8.2.2.3 Master Clock Input and Clock Multiplier
        4. 8.2.2.4 Temperature Measurement and Alarm Circuit
        5. 8.2.2.5 LVDS-Compatible I/Os
        6. 8.2.2.6 LVDS-Compatible Inputs
        7. 8.2.2.7 LVDS-Compatible Outputs
      3. 8.2.3 Application Curve
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
      3. 8.4.3 Thermal Considerations
  10. 9 Device and Documentation Support
    1. 9.1 Receiving Notification of Documentation Updates
    2. 9.2 Support Resources
    3. 9.3 Trademarks
    4. 9.4 Electrostatic Discharge Caution
    5. 9.5 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

5.8 Power Consumption

Typical conditions are at 55°C junction temperature, VCC = 3.3 V.
CONDITION CURRENT UNIT
TYP MAX
One channel plus sync, counter length = 18 bits, output interface speed = 75MHz 420 mA
As above with an additional channel add 125 mA
Output interface speed 150MHz add 10 mA
300MHz add 25
Counter length 27 bits add 60 mA
34 bits add 105
Four-channel current 18 bits 75MHz 795 1075 mA
150MHz 805 1090
300MHz 820 1101
27 bits 75MHz 855 1150
150MHz 865 1165
300MHz 880 1176
34 bits 75MHz 900 1210
150MHz 910 1225
300MHz 925 1236