SLOS510E September   2006  – October 2016 TLC082-Q1 , TLC084-Q1

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics: VDD = 5 V
    6. 6.6 Electrical Characteristics: VDD = 12 V
    7. 6.7 Operating Characteristics: VDD = 5 V
    8. 6.8 Operating Characteristics: VDD = 12 V
    9. 6.9 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 Macromodel Information
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 TLC08x-Q1 Single-Supply Typical Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
          1. 9.2.1.2.1 Driving a Capacitive Load
          2. 9.2.1.2.2 Offset Voltage
          3. 9.2.1.2.3 High-Speed CMOS Input Amplifiers
          4. 9.2.1.2.4 General Configurations
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Dual-Supply Typical Application
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 General PowerPAD™ Design Considerations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 Related Links
    3. 12.3 Receiving Notification of Documentsation Updates
    4. 12.4 Community Resources
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VDD Supply voltage(2) –0.3 17 V
VID Differential input voltage ±VDD V
Continuous total power dissipation See Thermal Information
TJ Operating junction temperature –40 125 °C
TA Operating ambient temperature –40 125 °C
TJ(max) Maximum junction temperature 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±2000 V
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (1, 4, 5, and 8) ±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

MIN MAX UNIT
VDD Supply voltage Single supply 4.5 16 V
Split supply ±2.25 ±8
VICR Common-mode input voltage GND VDD – 2 V
TJ Operating junction temperature –40 125 °C

6.4 Thermal Information

THERMAL METRIC(1) TLC082-Q1 TLC084-Q1 UNIT
DGN (MSOP-PowerPAD) PWP (HTSSOP)
8-PIN 20-PIN
RθJA Junction-to-ambient thermal resistance 58.1 40 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 55.2 46.7 °C/W
RθJB Junction-to-board thermal resistance 35.3 22.9 °C/W
ψJT Junction-to-top characterization parameter 2.1 1 °C/W
ψJB Junction-to-board characterization parameter 35.9 26.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 6.9 2.6 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: VDD = 5 V

VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ(1) MIN TYP MAX UNIT
VIO Input offset voltage VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω 25°C 390 1900 μV
Full range 3300
αVIO Temperature coefficient of input offset voltage VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω 1.2 μV/°C
IIO Input offset current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω 25°C 1.9 50 pA
Full range 700
IIB Input bias current VDD = 5 V, VIC = 2.5 V, VO = 2.5 V, RS = 50 Ω 25°C 3 50 pA
Full range 700
VICR Common-mode input voltage RS = 50 Ω 25°C 0 to 3 0 to 3.5 V
Full range 0 to 3 0 to 3.5
VOH High-level output voltage VIC = 2.5 V IOH = –1 mA 25°C 4.1 4.3 V
Full range 3.9
IOH = –20 mA 25°C 3.7 4
Full range 3.5
IOH = –35 mA 25°C 3.4 3.8
Full range 3.2
IOH = –50 mA 25°C 3.2 3.6
Full range 3
VOL Low-level output voltage VIC = 2.5 V IOL = 1 mA 25°C 0.18 0.25 V
Full range 0.35
IOL = 20 mA 25°C 0.35 0.39
Full range 0.45
IOL = 35 mA 25°C 0.43 0.55
Full range 0.7
IOL = 50 mA 25°C 0.45 0.63
Full range 0.7
IOS Short-circuit output current Sourcing 25°C 100 mA
Sinking 100
IO Output current VOH = 1.5 V from positive rail 25°C 57 mA
VOL = 0.5 V from negative rail 55
AVD Large-signal differential voltage amplification VO(PP) = 3 V, RL = 10 kΩ 25°C 100 120 dB
Full range 100
rj(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 10 kHz 25°C 22.9 pF
ZO Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω
CMRR Common-mode rejection ratio VIC = 0 to 3 V, RS = 50 Ω 25°C 70 110 dB
Full range 70
kSVR Supply voltage rejection ratio
(ΔVDD / ΔVIO)		 VDD = 4.5 V to 16 V, VIC = VDD/2, No load 25°C 80 100 dB
Full range 80
IDD Supply current (per channel) VO = 2.5 V, No load 25°C 1.8 2.5 mA
Full range 3.5
(1) Full range is –40°C to 125°C.

6.6 Electrical Characteristics: VDD = 12 V

VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ (1) MIN TYP MAX UNIT
VIO Input offset voltage VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω 25°C 390 1900 μV
Full range 3300
αVIO Temperature coefficient of input offset voltage VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω 1.2 μV/°C
IIO Input offset current VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω 25°C 1.5 50 pA
Full range 700
IIB Input bias current VDD = 12 V, VIC = 6 V, VO = 6 V, RS = 50 Ω 25°C 3 50 pA
Full range 700
VICR Common-mode input voltage RS = 50 Ω 25°C 0 to 10 0 to 10.5 V
Full range 0 to 10 0 to 10.5
VOH High-level output voltage VIC = 6 V IOH = –1 mA 25°C 11.1 11.2 V
Full range 11
IOH = –20 mA 25°C 10.8 11
Full range 10.7
IOH = –35 mA 25°C 10.6 10.7
Full range 10.3
IOH = –50 mA 25°C 10.3 10.5
Full range 10.1
VOL Low-level output voltage VIC = 6 V IOL = 1 mA 25°C 0.17 0.25 V
Full range 0.35
IOL = 20 mA 25°C 0.35 0.45
Full range 0.55
IOL = 35 mA 25°C 0.4 0.52
Full range 0.6
IOL = 50 mA 25°C 0.45 0.6
Full range 0.7
IOS Short-circuit output current Sourcing 25°C 150 mA
Sinking 150
IO Output current VOH = 1.5 V from positive rail 25°C 57 mA
VOL = 0.5 V from negative rail 55
AVD Large-signal differential voltage amplification VO(PP) = 8 V, RL = 10 kΩ 25°C 110 130 dB
Full range 110
rj(d) Differential input resistance 25°C 1000 GΩ
CIC Common-mode input capacitance f = 10 kHz 25°C 21.6 pF
ZO Closed-loop output impedance f = 10 kHz, AV = 10 25°C 0.25 Ω
CMRR Common-mode rejection ratio VIC = 0 to 10 V, RS = 50 Ω 25°C 80 110 dB
Full range 80
kSVR Supply voltage rejection ratio
(ΔVDD / ΔVIO)		 VDD = 4.5 V to 16 V, VIC = VDD / 2, No load 25°C 80 100 dB
Full range 80
IDD Supply current (per channel) VO = 7.5 V, No load 25°C 1.9 2.9 mA
Full range 3.5

6.7 Operating Characteristics: VDD = 5 V

VDD = 5 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ(1) MIN TYP MAX UNIT
SR+ Positive slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ 25°C 10 16 V/μs
Full range 9
SR– Negative slew rate at unity gain VO(PP) = 0.8 V, CL = 50 pF, RL = 10 kΩ 25°C 11 19 V/μs
Full range 8.5
Vn Equivalent input noise voltage f = 100 Hz 25°C 12 nV/√Hz
f = 1 kHz 8.5
In Equivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
THD+N Total harmonic distortion
plus noise		 VO(PP) = 3 V, RL = 10 kΩ and 250 Ω, f = 1 kHz AV = 1 25°C 0.002% —
AV = 10 0.012%
AV = 100 0.085%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz
ts Settling time V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ		 0.1% 25°C 0.18 μs
0.01% 0.39
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ		 0.1% 0.18
0.01% 0.39
φm Phase margin RL = 10 kΩ CL = 50 pF 25°C 32 °
CL = 0 pF 40
Gain margin RL = 10 kΩ CL = 50 pF 25°C 2.2 dB
CL = 0 pF 3.3
(1) Full range is –40°C to 125°C.

6.8 Operating Characteristics: VDD = 12 V

VDD = 12 V (unless otherwise noted)
PARAMETER TEST CONDITIONS TJ(1) MIN TYP MAX UNIT
SR+ Positive slew rate at unity gain VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ 25°C 10 16 V/μs
Full range 9.5
SR– Negative slew rate at unity gain VO(PP) = 2 V, CL = 50 pF, RL = 10 kΩ 25°C 12.5 19 V/μs
Full range 10
Vn Equivalent input noise voltage f = 100 Hz 25°C 14 nV/√Hz
f = 1 kHz 8.5
In Equivalent input noise current f = 1 kHz 25°C 0.6 fA/√Hz
THD+N Total harmonic distortion
plus noise		 VO(PP) = 8 V, RL = 10 kΩ and 250 Ω, f = 1 kHz AV = 1 25°C 0.002% —
AV = 10 0.005%
AV = 100 0.022%
Gain-bandwidth product f = 10 kHz, RL = 10 kΩ 25°C 10 MHz
ts Settling time V(STEP)PP = 1 V, AV = –1,
CL = 10 pF, RL = 10 kΩ		 0.1% 25°C 0.17 μs
0.01% 0.22
V(STEP)PP = 1 V, AV = –1,
CL = 47 pF, RL = 10 kΩ		 0.1% 0.17
0.01% 0.29
φm Phase margin RL = 10 kΩ CL = 50 pF 25°C 37 deg
CL = 0 pF 42
Gain margin RL = 10 kΩ CL = 50 pF 25°C 3.1 dB
CL = 0 pF 4

6.9 Typical Characteristics

Table 1. Table of Graphs

GRAPH NAME FIGURE NO.
VIO Input offset voltage vs Common-mode input voltage Figure 1, Figure 2
IIO Input offset current vs Free-air temperature Figure 3
IIB Input bias current vs Free-air temperature Figure 4
VOH High-level output voltage vs High-level output current Figure 5, Figure 7
VOL Low-level output voltage vs Low-level output current Figure 6, Figure 8
ZO Output impedance vs Frequency Figure 9
IDD Supply current vs Supply voltage Figure 10
PSRR Power supply rejection ratio vs Frequency Figure 11
CMRR Common-mode rejection ratio vs Frequency Figure 12
Vn Equivalent input noise voltage vs Frequency Figure 13
VO(PP) Peak-to-peak output voltage vs Frequency Figure 14, Figure 15
Crosstalk vs Frequency Figure 16
Differential voltage gain and Phase vs Frequency Figure 17, Figure 18
φm Phase margin vs Load capacitance Figure 19, Figure 20
Gain margin vs Load capacitance Figure 21, Figure 22
Gain-bandwidth product vs Supply voltage Figure 23
SR Slew rate vs Supply voltage Figure 24
vs Free-air temperature Figure 25, Figure 26
THD+N Total harmonic distortion plus noise vs Frequency Figure 27, Figure 28
vs Peak-to-peak output voltage Figure 29, Figure 30
Large-signal follower pulse response Figure 31, Figure 32
Small-signal follower pulse response Figure 33
Large-signal inverting pulse response Figure 34, Figure 34
Small-signal inverting pulse response Figure 36
TLC082-Q1 TLC084-Q1 g_vio_vicr_5v.gif
Figure 1. Input Offset Voltage
vs Common-Mode Input Voltage
TLC082-Q1 TLC084-Q1 g_iib_iio_ta_5v.gif
Figure 3. Input Bias Current and Input Offset Current
vs Free-Air Temperature
TLC082-Q1 TLC084-Q1 g_voh_ioh_5v.gif
Figure 5. High-Level Output Voltage
vs High-Level Output Current
TLC082-Q1 TLC084-Q1 g_voh_ioh_12v.gif
Figure 7. High-Level Output Voltage
vs High-Level Output Current
TLC082-Q1 TLC084-Q1 g_zo_freq.gif
Figure 9. Output Impedance vs Frequency
TLC082-Q1 TLC084-Q1 g_psrr_freq.gif
Figure 11. Power-Supply Rejection Ratio vs Frequency
TLC082-Q1 TLC084-Q1 g_vn_freq.gif
Figure 13. Equivalent Input Noise Voltage vs Frequency
TLC082-Q1 TLC084-Q1 g_vopp_freq_rl10k.gif
Figure 15. Peak-to-Peak Output Voltage vs Frequency
TLC082-Q1 TLC084-Q1 g_avd_ph_freq_2p5v.gif
Figure 17. Differential Voltage Gain and Phase
vs Frequency
TLC082-Q1 TLC084-Q1 g_pm_cl_5v.gif
Figure 19. Phase Margin vs Load Capacitance
TLC082-Q1 TLC084-Q1 g_gm_cl_5v.gif
Figure 21. Gain Margin vs Load Capacitance
TLC082-Q1 TLC084-Q1 g_gbwp_vdd.gif
Figure 23. Gain-Bandwidth Product vs Supply Voltage
TLC082-Q1 TLC084-Q1 g_sr_ta_5v.gif
Figure 25. Slew Rate vs Free-Air Temperature
TLC082-Q1 TLC084-Q1 g_thdn_freq_5v.gif
Figure 27. Total Harmonic Distortion + Noise vs Frequency
TLC082-Q1 TLC084-Q1 g_thdn_vopp_5v.gif
Figure 29. Total Harmonic Distortion Plus
Peak-to-Peak Output Voltage
TLC082-Q1 TLC084-Q1 g_lrg_flw_resp_5v.gif
Figure 31. Large-Signal Follower Pulse Response
TLC082-Q1 TLC084-Q1 g_sm_flw_resp.gif
Figure 33. Small-Signal Follower Pulse Response
TLC082-Q1 TLC084-Q1 g_lrg_inv_resp_12v.gif
Figure 35. Large-Signal Inverting Pulse Response
TLC082-Q1 TLC084-Q1 g_vio_vicr_12v.gif
Figure 2. Input Offset Voltage
vs Common-Mode Input Voltage
TLC082-Q1 TLC084-Q1 g_iib_iio_ta_12v.gif
Figure 4. Input Bias Current and Input Offset Current
vs Free-Air Temperature
TLC082-Q1 TLC084-Q1 g_vol_iol_5v.gif
Figure 6. Low-Level Output Voltage
vs Low-Level Output Current
TLC082-Q1 TLC084-Q1 g_vol_iol_12v.gif
Figure 8. Low-Level Output Voltage
vs Low-Level Output Current
TLC082-Q1 TLC084-Q1 g_idd_vdd.gif
Figure 10. Supply Current vs Supply Voltage
TLC082-Q1 TLC084-Q1 g_cmrr_freq.gif
Figure 12. Common-Mode Rejection Ration vs Frequency
TLC082-Q1 TLC084-Q1 g_vopp_freq_rl600.gif
Figure 14. Peak-to-Peak Output Voltage vs Frequency
TLC082-Q1 TLC084-Q1 g_xtalk_freq.gif
Figure 16. Crosstalk vs Frequency
TLC082-Q1 TLC084-Q1 g_avd_ph_freq_6v.gif
Figure 18. Differential Voltage Gain and Phase
vs Frequency
TLC082-Q1 TLC084-Q1 g_pm_cl_12v.gif
Figure 20. Phase Margin vs Load Capacitance
TLC082-Q1 TLC084-Q1 g_gm_cl_12v.gif
Figure 22. Gain Margin vs Load Capacitance
TLC082-Q1 TLC084-Q1 g_sr_vdd.gif
Figure 24. Slew Rate vs Supply Voltage
TLC082-Q1 TLC084-Q1 g_sr_ta_12v.gif
Figure 26. Slew Rate vs Free-Air Temperature
TLC082-Q1 TLC084-Q1 g_thdn_freq_12v.gif
Figure 28. Total Harmonic Distortion + Noise Frequency
TLC082-Q1 TLC084-Q1 g_thdn_vopp_12v.gif
Figure 30. Total Harmonic Distortion Plus
Peak-to-Peak Output Voltage
TLC082-Q1 TLC084-Q1 g_lrg_flw_resp_12v.gif
Figure 32. Large-Signal Follower Pulse Response
TLC082-Q1 TLC084-Q1 g_lrg_inv_resp_5v.gif
Figure 34. Large-Signal Follower Pulse Response
TLC082-Q1 TLC084-Q1 g_sm_inv_resp.gif
Figure 36. Small-Signal Inverting Pulse Response