SLFS043I September   1983  – July 2019 TLC555

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
    1.     Device Images
      1.      Simplified Schematic
  4. Revision History
  5. Pin Configuration and Functions
    1.     Pin Functions: D, P, PS, and JG Packages
    2.     Pin Functions: PW and FK
  6. Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 Recommended Operating Conditions
    3. 6.3 Thermal Information
    4. 6.4 Electrical Characteristics: VDD = 2 V for TLC555C, VDD = 3 V for TLC555I
    5. 6.5 Electrical Characteristics: VDD = 5 V
    6. 6.6 Electrical Characteristics: VDD = 15 V
    7. 6.7 Operating Characteristics
    8. 6.8 Typical Characteristics
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Monostable Operation
      2. 7.3.2 Astable Operation
      3. 7.3.3 Frequency Divider
    4. 7.4 Device Functional Modes
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Missing-Pulse Detector
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Pulse-Width Modulation
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Curve
      3. 8.2.3 Pulse-Position Modulation
        1. 8.2.3.1 Design Requirements
        2. 8.2.3.2 Detailed Design Procedure
        3. 8.2.3.3 Application Curves
      4. 8.2.4 Sequential Timer
        1. 8.2.4.1 Design Requirements
        2. 8.2.4.2 Detailed Design Procedure
        3. 8.2.4.3 Application Curve
      5. 8.2.5 Designing for Improved ESD Performance
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Receiving Notification of Documentation Updates
    2. 11.2 Community Resources
    3. 11.3 Trademarks
    4. 11.4 Electrostatic Discharge Caution
    5. 11.5 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Layout Guidelines

Standard PCB rules apply to routing the TLC555. The 0.1-μF ceramic capacitor in parallel with a 1-μF electrolytic capacitor must be as close as possible to the TLC555. The capacitor used for the time delay must also be placed as close to the discharge pin. A ground plane on the bottom layer can be used to provide better noise immunity and signal integrity.

Figure 28 is the basic layout for various applications.

  • C1—based on time delay calculations
  • C2—0.01-μF bypass capacitor for control voltage pin
  • C3—0.1-μF bypass ceramic capacitor
  • C4—1-μF electrolytic bypass capacitor
  • R1—based on time-delay calculations