TLC555

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2.1-MHz, 250-µA, Low-Power Timer

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Product details

Parameters

VCC (Min) (V) 2 VCC (Max) (V) 15 Iq (Typ) (uA) 250 Rating Catalog Operating temperature range (C) -40 to 125, -40 to 85, 0 to 70 open-in-new Find other Real-time clocks (RTCs) & timers

Package | Pins | Size

PDIP (P) 8 93 mm² 9.81 x 9.43 SOIC (D) 8 19 mm² 3.91 x 4.9 SOP (PS) 8 48 mm² 6.2 x 7.8 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other Real-time clocks (RTCs) & timers

Features

  • Very low power consumption:
    • 1-mW typical at VDD = 5 V
  • Capable of operation in astable mode
  • CMOS output capable of swinging rail to rail
  • High output current capability
    • Sink: 100-mA typical
    • Source: 10-mA typical
  • Output fully compatible with CMOS, TTL, and MOS
  • Low supply current reduces spikes during output transitions
  • Single-supply operation from 2 V to 15 V
  • Functionally interchangeable with the NE555; has same pinout
  • ESD protection exceeds 2000 V per MIL-STD-883C, method 3015.2
  • Available in Q-temp automotive
    • High-reliability automotive applications
    • Configuration control and print support
    • Qualification to automotive standards

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Description

The TLC555 is a monolithic timing circuit fabricated using the TI LinCMOS™ process. The timer is fully compatible with CMOS, TTL, and MOS logic and operates at frequencies up to 2 MHz. Because of its high input impedance, this device supports smaller timing capacitors than those supported by the NE555 or LM555. As a result, more accurate time delays and oscillations are possible. Power consumption is low across the full range of power-supply voltage.

Like the NE555, the TLC555 has a trigger level equal to approximately one-third of the supply voltage and a threshold level equal to approximately two-thirds of the supply voltage. These levels can be altered by use of the control voltage terminal (CONT). When the trigger input (TRIG) falls below the trigger level, the flip-flop is set and the output goes high. If TRIG is above the trigger level and the threshold input (THRES) is above the threshold level, the flip-flop is reset and the output is low. The reset input (RESET) can override all other inputs and can be used to initiate a new timing cycle. If RESET is low, the flip-flop is reset and the output is low. Whenever the output is low, a low-impedance path is provided between the discharge terminal (DISCH) and GND. All unused inputs must be tied to an appropriate logic level to prevent false triggering.

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Technical documentation

= Top documentation for this product selected by TI
No results found. Please clear your search and try again. View all 3
Type Title Date
* Datasheet TLC555 LinCMOS™ Timer datasheet (Rev. I) Jul. 05, 2019
More literature Design low-duty-cycle timer circuits Oct. 03, 2016
Application notes Synchronizing Three or More UCC28950 Phase-Shifted, Full-Bridge Controllers Sep. 13, 2011

Design & development

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Design tools & simulation

SIMULATION MODELS Download
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PSPICE-FOR-TI — PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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  • Leverages Cadence PSpice Technology
  • Preinstalled library with a suite of digital models to enable worst-case timing analysis
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  • Optimized for simulation speed without loss of accuracy
  • Supports simultaneous analysis of multiple products
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CAD/CAE symbols

Package Pins Download
PDIP (P) 8 View options
SO (PS) 8 View options
SOIC (D) 8 View options
TSSOP (PW) 14 View options

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