SLDS156B March   2009  – July 2015 TLC59108

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Description (continued)
  6. Pin Configuration and Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Open-Circuit Detection
      2. 9.3.2 Overtemperature Detection and Shutdown
      3. 9.3.3 Power-On Reset
      4. 9.3.4 External Reset
      5. 9.3.5 Software Reset
      6. 9.3.6 Individual Brightness Control With Group Dimming/Blinking
    4. 9.4 Device Functional Modes
    5. 9.5 Programming
      1. 9.5.1 Characteristics of the I2C Bus
        1. 9.5.1.1 Bit Transfer
        2. 9.5.1.2 Start and Stop Conditions
      2. 9.5.2 System Configuration
      3. 9.5.3 Acknowledge
      4. 9.5.4 Device Address
      5. 9.5.5 Regular I2C Bus Slave Address
      6. 9.5.6 LED All Call I2C Bus Address
      7. 9.5.7 LED Sub Call I2C Bus Address
      8. 9.5.8 Software Reset I2C Bus Address
      9. 9.5.9 Control Register
    6. 9.6 Register Maps
      1. 9.6.1 Register Descriptions
        1. 9.6.1.1  Mode Register 1 (MODE1)
        2. 9.6.1.2  Mode Register 2 (MODE2)
        3. 9.6.1.3  Brightness Control Registers 0 to 7 (PWM0 to PWM7)
        4. 9.6.1.4  Group Duty Cycle Control Register (GRPPWM)
        5. 9.6.1.5  Group Frequency Register (GRPFREQ)
        6. 9.6.1.6  LED Driver Output State Registers (LEDOUT0, LEDOUT1)
        7. 9.6.1.7  I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)
        8. 9.6.1.8  LED All Call I2C Bus Address Register (ALLCALLADR)
        9. 9.6.1.9  Output Gain Control Register (IREF)
        10. 9.6.1.10 Error Flags Registers (EFLAG)
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Driver Output
        1. 10.1.1.1 Constant Current Output
        2. 10.1.1.2 Adjusting Output Current
      2. 10.1.2 TLC59108 and TLC59108F Differences
    2. 10.2 Typical Application
      1. 10.2.1 Parallel Outputs
        1. 10.2.1.1 Design Requirements
        2. 10.2.1.2 Detailed Design Procedure
        3. 10.2.1.3 Application Curve
      2. 10.2.2 Multiple Devices
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Examples
  13. 13Device and Documentation Support
    1. 13.1 Community Resources
    2. 13.2 Trademarks
    3. 13.3 Electrostatic Discharge Caution
    4. 13.4 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

9 Detailed Description

9.1 Overview

The TLC59108 is an I2C bus controlled 8-bit LED driver that is optimized for red/green/blue/amber (RGBA) color mixing and backlight applications. Each LED output has its own 8-bit resolution (256 steps) fixed-frequency individual PWM controller that operates at 97 kHz, with a duty cycle that is adjustable from 0% to 99.6%. The individual PWM controller allows each LED to be set to a specific brightness value. An additional 8-bit resolution (256 steps) group PWM controller has both a fixed frequency of 190 Hz and an adjustable frequency between 24 Hz to once every 10.73 seconds, with a duty cycle that is adjustable from 0% to 99.6%. The group PWM controller dims or blinks all LEDs with the same value.

Each LED output can be off, on (no PWM control), or set at its individual PWM controller value at both individual and group PWM controller values.

The TLC59108 is one of the first LED controller devices in a new Fast-mode Plus (Fm+) family. Fm+ devices offer higher frequency (up to 1 MHz) and longer, more densely populated bus operation (up to 4000 pF).

Software programmable LED group and three Sub Call I2C bus addresses allow all or defined groups of TLC59108 devices to respond to a common I2C bus address, allowing for example, all red LEDs to be turned on or off at the same time or marquee chasing effect, thus minimizing I2C bus commands. Four hardware address pins allow up to 14 devices on the same bus.

The Software Reset (SWRST) call allows the master to perform a reset of the TLC59108 through the I2C bus, identical to the Power-On Reset (POR) that initializes the registers to their default state, causing the outputs to be set high (LED off). This allows an easy and quick way to reconfigure all device registers to the same condition.

9.2 Functional Block Diagram

TLC59108 fbd_lds156.gif

9.3 Feature Description

9.3.1 Open-Circuit Detection

The TLC59108 LED open-circuit detection compares the effective current level IOUT with the open load detection threshold current IOUT, Th. If IOUT is below the threshold IOUT, Th the TLC59108 detects an open load condition. This error status can be read out as an error flag through the EFLAG register.

For open-circuit error detection, a channel must be on.

Table 1. Open-Circuit Detection

STATE OF OUTPUT PORT CONDITION OF OUTPUT CURRENT ERROR STATUS CODE MEANING
Off IOUT = 0 mA 0 Detection not possible
On IOUT < IOUT,Th(1) 0 Open circuit
IOUT ≥ IOUT,Th(1) Channel n error status bit 1 Normal
(1) IOUT,Th = 0.5 × IOUT,target (typical)

9.3.2 Overtemperature Detection and Shutdown

The TLC59108 LED is equipped with a global overtemperature sensor and eight individual channel-selective overtemperature sensors.

  • When the global sensor reaches the trip temperature, all output channels are shutdown, and the error status is stored in the internal Error Status register of every channel. After shutdown, the channels automatically restart after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as the error status code in the EFLAG register.
  • When one of the channel-specific sensors reaches trip temperature, only the affected output channel is shut down, and the error status is stored only in the internal Error Status register of the affected channel. After shutdown, the channel automatically restarts after cooling down, if the control signal (output latch) remains on. The stored error status is not reset after cooling down and can be read out as error status code in the EFLAG register.

For channel-specific overtemperature error detection, a channel must be on.

The error flags of open-circuit and overtemperature are ORed to set the EFLAG register.

The error status code due to overtemperature is reset when the host writes 1 to bit 7 of the MODE2 register. The host must write 0 to bit 7 of the MODE2 register to enable the overtemperature error flag.

Table 2. Overtemperature Detection (1)

STATE OF OUTPUT PORT CONDITION ERROR STATUS CODE MEANING
On
On → all channels Off
TJ < TJ,trip global 1 Normal
TJ > TJ,trip global All error status bits = 0 Global overtemperature
On
On → Off
TJ < TJ,trip channel n 1 Normal
TJ > TJ,trip channel n Channel n error status bit = 0 Channel n overtemperature
(1) The global shutdown threshold temperature is approximately 170°C.

9.3.3 Power-On Reset

When power is applied to VCC, an internal power-on reset holds the TLC59108 in a reset condition until VCC reaches VPOR. At this point, the reset condition is released and the TLC59108 registers, and I2C bus state machine are initialized to their default states (all zeroes), causing all the channels to be deselected. Thereafter, VCC must be lowered below 0.2 V to reset the device.

9.3.4 External Reset

A reset can be accomplished by holding the RESET pin low for a minimum of tW. The TLC59108 registers and I2C state machine are held in their default states until the RESET input is again high.

This input requires a pullup resistor to VCC if no active connection is used.

9.3.5 Software Reset

The Software Reset Call (SWRST Call) allows all the devices in the I2C bus to be reset to the power-up state value through a specific I2C bus command. To be performed correctly, the I2C bus must be functional and there must be no device hanging the bus.

The SWRST Call function is defined as the following:

  1. A Start command is sent by the I2C bus master.
  2. The reserved SWRST I2C bus address 1001 011 with the R/W bit set to 0 (write) is sent by the I2C bus master.
  3. The TLC59108 device(s) acknowledge(s) after seeing the SWRST Call address 1001 0110 (96h) only. If the R/W bit is set to 1 (read), no acknowledge is returned to the I2C bus master.
  4. Once the SWRST Call address has been sent and acknowledged, the master sends two bytes with two specific values (SWRST data byte 1 and byte 2):
    1. Byte1 = A5h: the TLC59108 acknowledges this value only. If byte 1 is not equal to A5h, the TLC59108 does not acknowledge it.
    2. Byte 2 = 5Ah: the TLC59108 acknowledges this value only. If byte 2 is not equal to 5Ah, the TLC59108 does not acknowledge it.
  5. If more than two bytes of data are sent, the TLC59108 does not acknowledge any more.

  6. Once the correct two bytes (SWRST data byte 1 and byte 2 only) have been sent and correctly acknowledged, the master sends a Stop command to end the SWRST Call. The TLC59108 then resets to the default value (power-up value) and is ready to be addressed again within the specified bus free time (tBUF).

The I2C bus master may interpret a non-acknowledge from the TLC59108 (at any time) as a SWRST Call Abort. The TLC59108 does not initiate a reset of its registers. This happens only when the format of the Start Call sequence is not correct.

9.3.6 Individual Brightness Control With Group Dimming/Blinking

A 97-kHz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) is used to control the individual brightness for each LED.

On top of this signal, one of the following signals can be superimposed (this signal can be applied to the four LED outputs):

  • A lower 190-Hz fixed-frequency signal with programmable duty cycle (8 bits, 256 steps) provides a global brightness control.
  • A programmable frequency signal from 24 Hz to 1/10.73 s (8 bits, 256 steps) provides a global blinking control.
TLC59108 bright_groupdim_lds156.gif

NOTE:

Minimum pulse width for LEDn brightness control is 40 ns.
Minimum pulse width for group dimming is 20.48 μs.
When M = 1 (GRPPWM register value), the resulting LEDn Brightness Control + Group Dimming signal has two pulses of the LED Brightness Control signal (pulse width = n × 40 ns, with n defined in the PWMx register).
This resulting Brightness + Group Dimming signal shows a resulting control signal with n = 4 (8 pulses).
Figure 7. Brightness and Group Dimming Signals

9.4 Device Functional Modes

    Active Active mode occurs when one or more of the output channels is enabled.
    StandbyStandby mode occurs when all output channels are disabled. Standby mode may be entered via I2C command or by pulling the RESET pin low.

9.5 Programming

9.5.1 Characteristics of the I2C Bus

The I2C bus is for two-way two-line communication between different devices or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pullup resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.

9.5.1.1 Bit Transfer

One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the high period of the clock pulse as changes in the data line at this time are interpreted as control signals (see Figure 8).

TLC59108 bit_trans_lds156.gifFigure 8. Bit Transfer

9.5.1.2 Start and Stop Conditions

Both data and clock lines remain high when the bus is not busy. A high-to-low transition of the data line while the clock is high is defined as the Start condition (S). A low-to-high transition of the data line while the clock is high is defined as the Stop condition (P) (see Figure 9).

TLC59108 start_stop_lds156.gifFigure 9. Start and Stop Conditions

9.5.2 System Configuration

A device generating a message is a transmitter; a device receiving is the receiver. The device that controls the message is the master and the devices which are controlled by the master are the slaves (see Figure 10).

TLC59108 sys_config_lds156.gifFigure 10. System Configuration

9.5.3 Acknowledge

The number of data bytes transferred between the Start and the Stop conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a high level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse.

A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable low during the high period of the acknowledge related clock pulse; set-up time and hold time must be taken into account.

A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line high to enable the master to generate a Stop condition.

TLC59108 ack_nack_lds156.gifFigure 11. Acknowledge/Not Acknowledge on I2C Bus
TLC59108 write_one_reg_lds156.gifFigure 12. Write to a Specific Register
TLC59108 write_all_reg_lds156.gif
A. See Table 4 for register definitions.
Figure 13. Write to All Registers Using Auto-Increment
TLC59108 write_bright_reg_lds156.gifFigure 14. Multiple Writes to Individual Brightness Registers Using Auto-Increment
TLC59108 read_all_reg_lds156.gifFigure 15. Read All Registers Auto-Increment
TLC59108 led_all_call_lds156.gif
A. In this example, several TLC59108 devices are used, and the same Sequence A is sent to each of them.
B. The ALLCALL bit in the MODE1 register is equal to 1 for this example.
C. The OCH bit in the MODE2 register is equal to 1 for this example.
Figure 16. LED All Call I2C Bus Address Programming and LED All Call Sequence

9.5.4 Device Address

Following a Start condition, the bus master must output the address of the slave it is accessing.

9.5.5 Regular I2C Bus Slave Address

The I2C bus slave address of the TLC59108 is shown in Figure 17. To conserve power, no internal pullup resistors are incorporated on the hardware-selectable address pins, and they must be pulled high or low. For buffer management purpose, a set of sector information data should be stored.

TLC59108 slave_address_lds156.gifFigure 17. Slave Address

The last bit of the address byte defines the operation to be performed. When set to logic 1, a read operation is selected. When set to logic 0, a write operation is selected.

9.5.6 LED All Call I2C Bus Address

  • Default power-up value (ALLCALLADR register): 90h or 1001 000
  • Programmable through I2C bus (volatile programming)
  • At power-up, LED All Call I2C bus address is enabled. TLC59108 sends an ACK when 90h (R/W = 0) or 91h (R/W = 1) is sent by the master.

See LED All Call I2C Bus Address Register (ALLCALLADR) for more detail.

NOTE

The default LED All Call I2C bus address (90h or 1001 000) must not be used as a regular I2C bus slave address since this address is enabled at power-up. All the TLC59108 devices on the I2C bus acknowledge the address if sent by the I2C bus master.

9.5.7 LED Sub Call I2C Bus Address

  • Three different I2C bus address can be used
  • Default power-up values:
    • SUBADR1 register: 92h or 1001 001
    • SUBADR2 register: 94h or 1001 010
    • SUBADR3 register: 98h or 1001 100
  • Programmable through I2C bus (volatile programming)
  • At power-up, Sub Call I2C bus address is disabled. TLC59108 does not send an ACK when 92h (R/W = 0) or 93h (R/W = 1) or 94h (R/W = 0) or 95h (R/W = 1) or 98h (R/W = 0) or 99h (R/W = 1) is sent by the master.

See I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3) for more detail.

NOTE

The default LED Sub Call I2C bus address may be used as a regular I2C bus slave address as long as they are disabled.

9.5.8 Software Reset I2C Bus Address

The address shown in Figure 18 is used when a reset of the TLC59108 needs to be performed by the master. The software reset address (SWRST Call) must be used with R/W = 0. If R/W = 1, the TLC59108 does not acknowledge the SWRST. See Software Reset for more detail.

TLC59108 sw_reset_address_lds156.gifFigure 18. Software Reset Address

NOTE

The Software Reset I2C bus address is reserved address and cannot be use as regular I2C bus slave address or as an LED All Call or LED Sub Call address.

9.5.9 Control Register

Following the successful acknowledgment of the slave address, LED All Call address or LED Sub Call address, the bus master sends a byte to the TLC59108, which is stored in the Control register. The lowest 5 bits are used as a pointer to determine which register is accessed (D[4:0]). The highest 3 bits are used as Auto-Increment flag and Auto-Increment options (AI[2:0]).

TLC59108 control_reg_lds156.gifFigure 19. Control Register

When the Auto-Increment flag is set (AI2 = logic 1), the five low order bits of the Control register are automatically incremented after a read or write. This allows the user to program the registers sequentially. Four different types of Auto-Increment are possible, depending on AI1 and AI0 values.

Table 3. Auto-Increment Options

AI2 AI1 AI0 DESCRIPTION
0 0 0 No auto-increment
1 0 0 Auto-increment for all registers. D[4:0] roll over to 0 0000 after the last register (1 0001) is accessed.
1 0 1 Auto-increment for individual brightness registers only. D[4:0] roll over to 0 0010 after the last register (0 1001) is accessed.
1 1 0 Auto-increment for global control registers only. D[4:0] roll over to 0 1010 after the last register (0 1011) is accessed.
1 1 1 Auto-increment for individual and global control registers only. D[4:0] roll over to 0 0010 after the last register (0 1011) is accessed.

NOTE

Other combinations not shown in Table 3. (AI[2:0] = 001, 010 and 011) are reserved and must not be used for proper device operation.

IREF and EFLAG not included in Auto-Increment

AI[2:0] = 000 is used when the same register must be accessed several times during a single I2C bus communication, for example, changes the brightness of a single LED. Data is overwritten each time the register is accessed during a write operation.

AI[2:0] = 100 is used when all the registers must be sequentially accessed, for example, power-up programming.

AI[2:0] = 101 is used when the four LED drivers must be individually programmed with different values during the same I2C bus communication, for example, changing color setting to another color setting.

AI[2:0] = 110 is used when the LED drivers must be globally programmed with different settings during the same I2C bus communication, for example, global brightness or blinking change.

AI[2:0] = 111 is used when individually and global changes must be performed during the same I2C bus communication, for example, changing color and global brightness at the same time.

Only the 5 least significant bits D[4:0] are affected by the AI[2:0] bits.

When the Control register is written, the register entry point determined by D[4:0] is the first register that is addressed (read or write operation), and can be anywhere between 0 0000 and 1 0001 (as defined in Table 4). When AI[2] = 1, the Auto-Increment flag is set and the rollover value at which the point where the register increment stops and goes to the next one is determined by AI[2:0]. See Table 3 for rollover values. For example, if the Control register = 1110 1100 (ECh), then the register addressing sequence is (in hex):

0C → ... → 11 → 00 → ... → 0B → 02 → ... → 0B → 02 → ... as long as the master keeps sending or reading data.

9.6 Register Maps

9.6.1 Register Descriptions

Table 4 describes the registers in the TLC59108.

Table 4. Register Descriptions

REGISTER NUMBER
(HEX)
NAME ACCESS (1) DESCRIPTION
00 MODE1 R/W Mode 1
01 MODE2 R/W Mode 2
02 PWM0 R/W Brightness control LED0
03 PWM1 R/W Brightness control LED1
04 PWM2 R/W Brightness control LED2
05 PWM3 R/W Brightness control LED3
06 PWM4 R/W Brightness control LED4
07 PWM5 R/W Brightness control LED5
08 PWM6 R/W Brightness control LED6
09 PWM7 R/W Brightness control LED7
0A GRPPWM R/W Group duty cycle control
0B GRPFREQ R/W Group frequency
0C LEDOUT0 R/W LED output state 0
0D LEDOUT1 R/W LED output state 1
0E SUBADR1 R/W I2C bus subaddress 1
0F SUBADR2 R/W I2C bus subaddress 2
10 SUBADR3 R/W I2C bus subaddress 3
11 ALLCALLADR R/W LED All Call I2C bus address
12 IREF R/W IREF configuration
13 EFLAG R Error flag
(1) R = read, W = write

9.6.1.1 Mode Register 1 (MODE1)

Table 5 describes Mode Register 1.

Table 5. MODE1 – Mode Register 1 (Address 00h) Bit Description

BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
7 AI2 R 0 (1) Register Auto-Increment disabled
1 Register Auto-Increment enabled
6 AI1 R 0 (1) Auto-Increment bit 1 = 0
1 Auto-Increment bit 1 = 1
5 AI0 R 0 (1) Auto-Increment bit 0 = 0
1 Auto-Increment bit 0 = 1
4 OSC R/W 0 Normal mode (2)
1 (1) Oscillator off (3).
3 SUB1 R/W 0 (1) Device does not respond to I2C bus subaddress 1.
1 Device responds to I2C bus subaddress 1.
2 SUB2 R/W 0 (1) Device does not respond to I2C bus subaddress 2.
1 Device responds to I2C bus subaddress 2.
1 SUB3 R/W 0 (1) Device does not respond to I2C bus subaddress 3.
1 Device responds to I2C bus subaddress 3.
0 ALLCALL R/W 0 Device does not respond to LED All Call I2C bus address.
1 (1) Device responds to LED All Call I2C bus address.
(1) Default value
(2) Requires 500 μs maximum for the oscillator to be up and running once SLEEP bit has been set to logic 1. Timings on LED outputs are not guaranteed if PWMx, GRPPWM, or GRPFREQ registers are accessed within the 100 μs window.
(3) No blinking or dimming is possible when the oscillator is off.

9.6.1.2 Mode Register 2 (MODE2)

Table 6 describes Mode Register 2.

Table 6. MODE2 – Mode Register 2 (Address 01h) Bit Description

BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
7 EFCLR R/W 0 (1) Enable error status flag
1 Clear error status flag
6 R 0 (1) Reserved
5 DMBLNK R/W 0 (1) Group control = dimming
1 Group control = blinking
4 R 0 (1) Reserved
3 OCH R/W 0 (1) Outputs change on Stop command (1)
1 Outputs change on ACK
2:0 R 000 (1) Reserved
(1) Change of the outputs at the Stop command allows synchronizing outputs of more than one TLC59108. Applicable to registers from 02h (PWM0) to 0Dh (LEDOUT) only.

9.6.1.3 Brightness Control Registers 0 to 7 (PWM0 to PWM7)

Table 7 describes Brightness Control Registers 0 to 7.

Table 7. PWM0 to PWM7 – PWM Registers 0 to 7 (Address 02h to 09h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
02h PWM0 7:0 IDC0[7:0] R/W 0000 0000 (1) PWM0 individual duty cycle
03h PWM1 7:0 IDC1[7:0] R/W 0000 0000 (1) PWM1 individual duty cycle
04h PWM2 7:0 IDC2[7:0] R/W 0000 0000 (1) PWM2 individual duty cycle
05h PWM3 7:0 IDC3[7:0] R/W 0000 0000 (1) PWM3 individual duty cycle
06h PWM4 7:0 IDC4[7:0] R/W 0000 0000 (1) PWM4 individual duty cycle
07h PWM5 7:0 IDC5[7:0] R/W 0000 0000 (1) PWM5 individual duty cycle
08h PWM6 7:0 IDC6[7:0] R/W 0000 0000 (1) PWM6 individual duty cycle
09h PWM7 7:0 IDC7[7:0] R/W 0000 0000 (1) PWM7 individual duty cycle

A 97-kHz fixed frequency signal is used for each output. Duty cycle is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = LED output at maximum brightness). Applicable to LED outputs programmed with LDRx = 10 or 11 (LEDOUT0 and LEDOUT1 registers).

Duty cycle = IDCn[7:0] / 256

9.6.1.4 Group Duty Cycle Control Register (GRPPWM)

Table 8 describes the Group Duty Cycle Control Register.

Table 8. GRPPWM – Group Brightness Control Register (Address 0Ah) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
0Ah GRPPWM 7:0 GDC0[7:0] R/W 1111 1111 (1) GRPPWM register

When the DMBLNK bit (MODE2 register) is programmed with logic 0, a 190-Hz fixed-frequency signal is superimposed with the 97-kHz individual brightness control signal. GRPPWM is then used as a global brightness control, allowing the LED outputs to be dimmed with the same value. The value in GRPFREQ is then a Don't care.

General brightness for the eight outputs is controlled through 256 linear steps from 00h (0% duty cycle = LED output off) to FFh (99.6% duty cycle = maximum brightness). Applicable to LED outputs programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

When DMBLNK bit is programmed with logic 1, the GRPPWM and GRPFREQ registers define a global blinking pattern, where GRPFREQ defines the blinking period (from 24 Hz to 10.73 s) and GRPPWM defines the duty cycle (ON/OFF ratio in %).

Duty cycle = GDC0[7:0] / 256

9.6.1.5 Group Frequency Register (GRPFREQ)

Table 9 describes the Group Frequency Register.

Table 9. GRPFREQ – Group Frequency Register (Address 0Bh) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
0Bh GRPFREQ 7:0 GFRQ[7:0] R/W 0000 0000 (1) GRPFREQ register

GRPFREQ is used to program the global blinking period when the DMBLNK bit (MODE2 register) is equal to 1. Value in this register is a Don't care when DMBLNK = 0. Applicable to LED output programmed with LDRx = 11 (LEDOUT0 and LEDOUT1 registers).

Blinking period is controlled through 256 linear steps from 00h (41 ms, frequency 24 Hz) to FFh (10.73 s).

Global blinking period (seconds) = (GFRQ[7:0] + 1) / 24

9.6.1.6 LED Driver Output State Registers (LEDOUT0, LEDOUT1)

Table 10 describes LED Driver Output State Registers 0 and 1.

Table 10. LEDOUT0 and LEDOUT1 – LED Driver Output State Registers (Address 0Ch and 0Dh) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
0Ch LEDOUT0 7:6 LDR3[1:0] R/W 00 (1) LED3 output state control
5:4 LDR2[1:0] R/W 00 (1) LED2 output state control
3:2 LDR1[1:0] R/W 00 (1) LED1 output state control
1:0 LDR0[1:0] R/W 00 (1) LED0 output state control
0Dh LEDOUT1 7:6 LDR7[1:0] R/W 00 (1) LED7 output state control
5:4 LDR6[1:0] R/W 00 (1) LED6 output state control
3:2 LDR5[1:0] R/W 00 (1) LED5 output state control
1:0 LDR4[1:0] R/W 00 (1) LED4 output state control

LDRx = 00: LED driver x is off (default power-up state).

LDRx = 01: LED driver x is fully on (individual brightness and group dimming/blinking not controlled).

LDRx = 10: LED driver x is individual brightness can be controlled through its PWMx register.

LDRx = 11: LED driver x is individual brightness and group dimming/blinking can be controlled through its PWMx register and the GRPPWM registers.

9.6.1.7 I2C Bus Subaddress Registers 1 to 3 (SUBADR1 to SUBADR3)

Table 11 describes I2C Bus Subaddress Registers 1 to 3.

Table 11. SUBADR1 to SUBADR3 – I2C Bus Subaddress Registers 1 to 3 (Address 0Eh to 10h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
0Eh SUBADR1 7:5 A1[7:5] R 100 (1) Reserved
4:1 A1[4:1] R/W 1001 (1) I2C bus subaddress 1
0 A1[0] R 0 (1) Reserved
0Fh SUBADR2 7:5 A2[7:1] R 100 (1) Reserved
4:1 A2[4:1] R/W 1010 (1) I2C bus subaddress 2
0 A2[0] R 0 (1) Reserved
10h SUBADR3 7:5 A3[7:1] R 100 (1) Reserved
4:1 A3[4:1] R/W 1100 (1) I2C bus subaddress 3
0 A3[0] R 0 (1) Reserved

Subaddresses are programmable through the I2C bus. Default power-up values are 92h, 94h, 98h. The TLC59108 does not acknowledge these addresses immediately after power-up (the corresponding SUBx bit in MODE1 register is equal to 0).

Once subaddresses have been programmed to valid values, the SUBx bits (MODE1 register) must be set to 1 to allows the device to acknowledge these addresses.

Only the 7 MSBs representing the I2C bus subaddress are valid. The LSB in SUBADRx register is a read-only bit (0).

When SUBx is set to 1, the corresponding I2C bus subaddress can be used during either an I2C bus read or write sequence.

9.6.1.8 LED All Call I2C Bus Address Register (ALLCALLADR)

Table 12 describes the LED All Call I2C Bus Address Register.

Table 12. ALLCALLADR – LED All Call I2C Bus Address Register (Address 11h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
11h ALLCALLADR 7:5 AC[7:5] R 100 (1) Reserved
4:1 AC[4:1] R/W 1000 (1) All Call I2C bus address register
0 AC[0] R 0 (1) Reserved

The LED All Call I2C bus address allows all the TLC59108 devices in the bus to be programmed at the same time (ALLCALL bit in register MODE1 must be equal to 1, which is the power-up default state). This address is programmable through the I2C bus and can be used during either an I2C bus read or write sequence. The register address can also be programmed as a Sub Call.

Only the 7 MSBs representing the All Call I2C bus address are valid. The LSB in ALLCALLADR register is a read-only bit (0).

If ALLCALL bit = 0, the device does not acknowledge the address programmed in register ALLCALLADR.

9.6.1.9 Output Gain Control Register (IREF)

Table 13 describes the Output Gain Control Register.

Table 13. IREF – Output Gain Control Register (Address 12h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
12h IREF 7 CM R/W 1 (1) High/low current multiplier
6 HC R/W 1 (1) Subcurrent
5:0 CC[5:0] R/W 11 1111 (1) Current multiplier

IREF determines the voltage gain (VG), which affects the voltage at the REXT terminal and indirectly the reference current (IREF) flowing through the external resistor at terminal REXT. Bit 0 is the Current Multiplier (CM) bit, which determines the ratio IOUT,target/Iref. Each combination of VG and CM sets a Current Gain (CG).

  • VG: the relationship between \{HC,CC[0:5]\} and the voltage gain is calculated as shown below:
  • VG = (1 + HC) × (1 + D/64) / 4

    D = CC0 × 25 + CC1 × 24 + CC2 × 23 + CC3 × 22 + CC4 × 21 + CC5 × 20

    Where HC is 1 or 0, and D is the binary value of CC[0:5]. So, the VG could be regarded as a floating-point number with 1-bit exponent HC and 6-bit mantissa CC[0:5]. \{HC,CC[0:5]\} divides the programmable voltage gain VG into 128 steps and two sub-bands:

    Low voltage sub-band (HC = 0): VG = 1/4 to 127/256, linearly divided into 64 steps

    High voltage sub-band (HC = 1): VG = 1/2 to 127/128, linearly divided into 64 steps

  • CM: In addition to determining the ratio IOUT,target/Iref, CM limits the output current range.
  • High Current Multiplier (CM = 1): IOUT,target/Iref = 15, suitable for output current range IOUT = 10 mA to 120 mA.

    Low Current Multiplier (CM = 0): IOUT,target/Iref = 5, suitable for output current range IOUT = 5 mA to 40 mA

  • CG: The total Current Gain is defined as the following.
  • VREXT = 1.26 V × VG

    Iref = VREXT/Rext, if the external resistor, Rext, is connected to ground.

    IOUT,target = Iref × 15 × 3CM – 1 = 1.26 V/Rext × VG × 15 × 3CM – 1 = (1.26 V/Rext × 15) × CG

    CG = VG × 3CM – 1

    Therefore, CG = (1/12) to (127/128), and it is divided into 256 steps. If CG = 127/128 = 0.992, the IOUT,target-Rext.

Examples

  • IREF Code \{CM, HC, CC[0:5]\} = \{1,1,111111\}
  • VG = 127/128 = 0.992 and CG = VG × 30 = VG = 0.992

  • IREF Code \{CM, HC, CC[0:5]\} = \{1,1,000000\}
  • VG = (1 + 1) × (1 + 0/64)/4 = 1/2 = 0.5, and CG = 0.5

  • IREF Code \{CM, HC, CC[0:5]\} = \{0,0,000000\}
  • VG = (1 + 0) × (1 + 0/64)/4 = 1/4, and CG = (1/4) × 3–1 = 1/12

After power on, the default value of the Configuration Code \{CM, HC, CC[0:5]\} is \{1,1,111111\}. Therefore, VG = CG = 0.992. The relationship between the Configuration Code and the Current Gain is shown in Figure 20.

TLC59108 currgain_configcode_lds156.gifFigure 20. Current Gain vs Configuration Code

9.6.1.10 Error Flags Registers (EFLAG)

Table 14 describes the Error Flags Register.

Table 14. EFLAG – Error Flags Register (Address 13h) Bit Description

ADDRESS REGISTER BIT SYMBOL ACCESS (1) VALUE DESCRIPTION
13h EFLAG 7:0 EFLAG[7:0] R 1111 1111 (1) Error flag status by channel