SLVSJD7 February   1997  – July 2025 TLE2021 , TLE2021A , TLE2021M , TLE2022 , TLE2022A , TLE2022AM , TLE2022M , TLE2024 , TLE2024A , TLE2024B , TLE2024BM

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Device Comparison Tables
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Recommended Operating Conditions
    3. 6.3  Thermal Information for TLE2021
    4. 6.4  Thermal Information for TLE2022
    5. 6.5  Thermal Information for TLE2024
    6. 6.6  Electrical Characteristics for TLE2021, VCC = ±15V
    7. 6.7  Electrical Characteristics for TLE2021, VCC = 5V
    8. 6.8  Electrical Characteristics for TLE2022, VCC = ±15V
    9. 6.9  Electrical Characteristics for TLE2022, VCC = 5V
    10. 6.10 Electrical Characteristics for TLE2024, VCC = ±15V
    11. 6.11 Electrical Characteristics for TLE2024, VCC = 5V
    12. 6.12 Typical Characteristics
  8. 7 Application and Implementation
    1. 7.1 Application Information
      1. 7.1.1 Voltage-Follower Applications
      2. 7.1.2 Input Offset Voltage Null
    2. 7.2 Layout
      1. 7.2.1 Layout Guidelines
      2. 7.2.2 Layout Example
  9. 8 Device and Documentation Support
    1. 8.1 Device Support
      1. 8.1.1 Device Nomenclature
    2. 8.2 Receiving Notification of Documentation Updates
    3. 8.3 Support Resources
    4. 8.4 Trademarks
    5. 8.5 Electrostatic Discharge Caution
    6. 8.6 Glossary
  10. 9 Revision History
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • D|8
Thermal pad, mechanical data (Package|Pins)
Orderable Information

7.2.1 Layout Guidelines

For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:

  1. Connect low-ESR, 0.1µF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible. A single bypass capacitor from VCC+ to ground is applicable for single-supply applications. Noise propagates into analog circuitry through the power pins of the circuit as a whole, as well as through the individual op amp. Use bypass capacitors to reduce the coupled noise by providing low-impedance power sources local to the analog circuitry.
  2. Physically separate digital and analog grounds, paying special attention to the ground-current flow. Separate grounding for analog and digital portions of circuitry is one of the simplest and most effective methods of noise suppression. One or more layers on multilayer PCBs are typically devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup.
  3. To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed to in parallel with the noisy trace.
  4. Place the external components as close to the device as possible. Figure 7-4 shows how to keep RF and RG close to the inverting input to minimize parasitic capacitance.
  5. Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit.
  6. Consider a driven, low-impedance guard ring around the critical traces. Use a guard ring to significantly reduce leakage currents from nearby traces that are at different potentials.
  7. Clean the PCB following board assembly for best performance.
  8. Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic package. After any aqueous PCB cleaning process, bake the PCB assembly to remove moisture introduced into the device packaging during the cleaning process. A low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.