SLVS647J August   2006  – May 2025 TLE4275-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Recommended Operating Conditions
    4. 5.4 Thermal Information
    5. 5.5 Electrical Characteristics
    6. 5.6 Timing Diagrams
    7. 5.7 Typical Characteristics
  7. 6 Parameter Measurement Information
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagrams
    3. 7.3 Feature Description
      1. 7.3.1 Power-Good Reset (RESET)
      2. 7.3.2 Adjustable Power-Good RESET Delay Timer (DELAY)
        1. 7.3.2.1 Setting the Adjustable Power-Good Reset Delay
      3. 7.3.3 Undervoltage Lockout
      4. 7.3.4 Current Limit
      5. 7.3.5 Thermal Shutdown
    4. 7.4 Device Functional Modes
      1. 7.4.1 Normal Operation
      2. 7.4.2 Dropout Operation
      3. 7.4.3 Disabled
  9. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 Input and Output Capacitor Selection
        1. 8.1.1.1 Legacy Chip Capacitor Selection
        2. 8.1.1.2 New Chip Capacitor Selection
          1. 8.1.1.2.1 Output Capacitor
          2. 8.1.1.2.2 Input Capacitor
      2. 8.1.2 Dropout Voltage
      3. 8.1.3 Reverse Current
      4. 8.1.4 Power Dissipation (PD)
        1. 8.1.4.1 Thermal Performance Versus Copper Area
        2. 8.1.4.2 Power Dissipation Versus Ambient Temperature
      5. 8.1.5 Estimating Junction Temperature
      6. 8.1.6 Setting the Adjustable Power-Good Reset Delay
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Capacitor
        2. 8.2.2.2 Output Capacitor
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Examples
  10. 9 Device and Documentation Support
    1. 9.1 Device Support
      1. 9.1.1 Device Nomenclature
      2. 9.1.2 Development Support
    2. 9.2 Documentation Support
      1. 9.2.1 Related Documentation
    3. 9.3 Receiving Notification of Documentation Updates
    4. 9.4 Support Resources
    5. 9.5 Trademarks
    6. 9.6 Electrostatic Discharge Caution
    7. 9.7 Glossary
  11. 10Revision History
  12. 11Mechanical, Packaging, and Orderable Information

Package Options

Refer to the PDF data sheet for device specific package drawings

Mechanical Data (Package|Pins)
  • KTT|5
  • PWP|20
  • KVU|5
Thermal pad, mechanical data (Package|Pins)
Orderable Information

8.2.3 Application Curves

legacy chip: IOUT = 200mA, CIN = 22µF, and COUT = 10µF; new chip: specified at TJ = –40°C to +150°C, VIN = 13.5V, IOUT = 100µA, COUT = 2.2µF, 1mΩ < COUT ESR < 2Ω, and CIN = 1µF (unless otherwise noted)

TLE4275-Q1 Power-Up Waveform (Legacy Chip)
Channel 1 = VOUT, channel 2 = VIN, channel 3 = VRESET
Figure 8-6 Power-Up Waveform (Legacy Chip)
TLE4275-Q1 Power-Supply Ripple Rejection vs Frequency and IOUT (New Chip)
COUT = 10µF (X7R 50V), VOUT = 5V
Figure 8-8 Power-Supply Ripple Rejection vs Frequency and IOUT (New Chip)
TLE4275-Q1 Start-Up Plot Inrush Current
VIN = 13.5V, VOUT = 5V, IOUT = 150mA, COUT = 10µF
Figure 8-10 Start-Up Plot Inrush Current
TLE4275-Q1 Power-Down Waveform (Legacy Chip)
Channel 1 = VOUT, channel 2 = VIN, channel 3 = VRESET
Figure 8-7 Power-Down Waveform (Legacy Chip)
TLE4275-Q1 Load Transient, 150mA to 350mA (New Chip)
VOUT = 5V, IOUT = 150mA to 350mA, slew rate = 0.1A/µs,
COUT = 10µF
Figure 8-9 Load Transient, 150mA to 350mA (New Chip)